# US 10,122,485 B2 · Signal processing apparatus and signal processing method

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- Number: US 10,122,485 B2
- Document ID: US10122485B2
- Status: Granted
- Kind: B2
- Application number: 15/037,739
- Filed: 2014-11-17
- Published: 2016-10-13
- Granted: 2018-11-06
- Earliest claimed: 2013-11-27
- Assignees: Sony Semiconductor Solutions Corporation
- Applicants: Sony Corporation
- Inventors: Naoki Yoshimochi; Satoshi Okada; Misa Nakane
- Web page: https://patentgrep.com/patent/US10122485B2

## CPC

- H04J 3/0658: {Clock or time synchronisation among packet nodes}
- H04B 7/08: at the receiving station
- H04W 4/06: Selective distribution of broadcast services, e.g. multimedia broadcast multicast service [MBMS]; Services to user groups; One-way selective calling services
- H04W 56/001: {Synchronization between nodes}
- H04J 2011/0013: {with TDM/TDMA}
- H04J 2011/0096: {Network synchronisation}
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)
- H04B: TRANSMISSION
- H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72)

## Abstract

The present technology relates to a signal processing apparatus, a signal processing method, and a program capable of reducing the number of pins for transmitting and receiving data. The signal processing apparatus is provided with a signal transmission unit configured to perform classification for a signal to be transmitted and received between processing units that process an obtained signal, perform time division multiplexing for the signal classified into a group, and transmit the signal. The classification is performed depending on at least one feature of an update period, an update timing, and a tolerable transmission delay of the signal. Further, the signal belonging to the group is subjected to time division multiplexing in such a manner that the transmission is completed within the update period, the transmission is completed within a range of the tolerable delay, and the transmission is performed with a minimum number of pins. The present technology can be applied to a reception apparatus that receives and processes airwaves.

## Claims

### Claim 1

A signal processing apparatus, comprising
a signal transmission unit configured to:
classify, into a group, at least one signal of a plurality of signals,
wherein the at least one signal is communicated between a first processing unit and a second processing unit, and
wherein the second processing unit processes the at least one signal;
execute a time division multiplexing operation on the at least one signal in the classified group,
wherein the at least one signal is transmitted, from the first processing unit to the second processing unit, within an updated period and in a range of tolerable delay, and
wherein the at least one signal is further transmitted, from the first processing unit to the second processing unit, with a minimum number of pins; and
transmit the at least one signal to the first processing unit.

### Claim 2 (depends on 1)

The signal processing apparatus according to claim 1, wherein the classification is based on at least one of: the update period, an update timing, and the range of tolerable delay of the at least one signal.

### Claim 3 (depends on 1)

The signal processing apparatus according to claim 1,
wherein the plurality of signals are transmitted within the update period and within the range of tolerable delay, and
wherein the plurality of signals are transmitted with the same pin.

### Claim 4 (depends on 1)

The signal processing apparatus according to claim 1, wherein the classified group includes:
a first group that comprises an enable signal,
a second group that comprises a first signal,
wherein the first signal is synchronized with the enable signal,
a third group that comprises a second signal,
wherein a first update period of the second signal is changed at an irregular interval, and
a fourth group that comprises a third signal,
wherein a second update period of the third signal is unchanged.

### Claim 5 (depends on 1)

The signal processing apparatus according to claim 1, wherein the classified group includes:
a first group that comprises an enable signal,
a second group that comprises:
data and a start flag of each sub carrier of OFDM, and
a first signal that requires a plurality of data transmissions in one symbol of OFDM,
a third group that comprises a second signal that indicates an internal state, and
a fourth group that comprises a third signal that indicates a broadcasting parameter.

### Claim 6 (depends on 5)

The signal processing apparatus according to claim 5, wherein
the enable signal of the first group is transmitted with one pin,
the first signal of the second group is transmitted with a plurality of pins,
the second signal and the third signal are transmitted with the same number of pins.

### Claim 7 (depends on 1)

The signal processing apparatus according to claim 1, wherein
the at least one signal is communicated, between the first processing unit and the second processing unit, unidirectionally, and
a clock is communicated, between the first processing unit and the second processing unit, unidirectionally.

### Claim 8 (depends on 1)

The signal processing apparatus according to claim 1, wherein
the at least one signal is communicated, between the first processing unit and the second processing unit, bidirectionally, and
a clock is communicated, between the first processing unit and the second processing unit, bidirectionally.

### Claim 9 (depends on 1)

The signal processing apparatus according to claim 1, wherein
the at least one signal is communicated, between the first processing unit and the second processing unit, bidirectionally, and
a clock is communicated, between the first processing unit and the second processing unit, unidirectionally.

### Claim 10 (depends on 1)

The signal processing apparatus according to claim 1, further comprising a clock generation unit configured to:
generate a clock signal, and
supply the clock signal to the first processing unit and the second processing unit,
wherein the first processing unit and the second processing unit are operated based on a clock.

### Claim 11 (depends on 1)

The signal processing apparatus according to claim 1,
wherein the second processing unit receives the at least one signal transmitted from the first processing unit,
wherein the second processing unit changes a first clock, transmitted from the first processing unit, to a second clock, and
wherein the second clock is generated by the second processing unit.

### Claim 12

A signal processing method, comprising the steps of:
classifying, into a group, a signal communicated between a first processing unit and a second processing unit,
wherein the second processing unit processes the signal; and
executing a time division multiplexing operation on the signal in the classified group,
wherein the signal is transmitted, from the first processing unit to the second processing unit, within an updated period and in a range of tolerable delays, and
wherein the signal is further transmitted, from the first processing unit to the second processing unit, with a minimum number of pins; and
transmitting the signal to the first processing unit.

### Claim 13

A non-transitory computer-readable medium having stored thereon computer-executable instructions that, when executed by a computer, cause the computer to execute operations, the operations comprising:
classifying, into a group, a signal communicated between a first processing unit and a second processing unit,
wherein the second processing unit processes the signal; and
executing a time division multiplexing operation on the signal in the classified group,
wherein the signal is transmitted, from the first processing unit to the second processing unit, within an updated period and in a range of tolerable delays, and
wherein the signal is further transmitted, from the first processing unit to the second processing unit, with a minimum number of pins; and
transmitting the signal to the first processing unit.
