# US 10,122,392 B2 · Active equalizing negative resistance amplifier for bi-directional bandwidth extension > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,122,392 B2 - Document ID: US10122392B2 - Status: Granted - Kind: B2 - Application number: 15/240,549 - Filed: 2016-08-18 - Published: 2018-02-22 - Granted: 2018-11-06 - Earliest claimed: 2016-08-18 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: Milam Paraschou; Gerald R. Talbot; Dean E. Gonzales - Web page: https://patentgrep.com/patent/US10122392B2 ## CPC - H04B 1/0475: {with means for limiting noise, interference or distortion (H04B1/0483 takes precedence)} - H03F 3/45475: {using IC blocks as the active amplifying circuit} - H03H 11/52: simulating negative resistances - H03F 2200/369: A negative impedance circuit being added to an amplifier circuit - H03F 2203/45034: One or more added reactive elements, capacitive or inductive elements, to the amplifying transistors in the differential amplifier - H03F 2203/45134: the whole differential amplifier together with other coupled stages being fully differential realised - H03F 2203/45138: Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers - H04B: TRANSMISSION - H03F: AMPLIFIERS - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) ## Abstract Systems, apparatuses, and methods for implementing a negative resistance circuit for bandwidth extension are disclosed. Within a feedback path of a differential signal path, capacitors are placed on the inputs and outputs of a fully differential amplifier connecting to the differential signal path. In one embodiment, a circuit includes a fully differential amplifier and four capacitors. A first capacitor is coupled between a first signal path and a non-inverting input terminal of the amplifier and a second capacitor is coupled between the first signal path and a non-inverting output terminal of the amplifier. A third capacitor is coupled between a second signal path and an inverting input terminal of the amplifier and a fourth capacitor is coupled between the second signal path and an inverting output terminal of the amplifier. The first and second signal paths carry a differential signal. ## Claims ### Claim 1 An apparatus for bandwidth extension, the apparatus comprising: a first amplifier; and a plurality of capacitors; a first multiplexor configured to select which one of a first plurality of signal paths is connected to a first signal path, and a second multiplexer configured to select which one of a second plurality of signal paths is connected to a second signal path, wherein each of the first signal path and second signal path is connected to a pad that is connected to a USB connector, wherein a first signal received by the first multiplexer is compliant with a universal serial bus protocol, and wherein a second signal received by the first multiplexer is compliant with a DisplayPort protocol; wherein the apparatus is configured to: receive a first signal component of a differential signal on a first signal path; pass the first signal component through a first capacitor to a non-inverting input terminal of a first amplifier; receive a second signal component of the differential signal on a second signal path; and pass the second signal component through a second capacitor to an inverting input terminal of the first amplifier; and wherein the first signal is generated by a first physical layer (PHY) logical unit, the second signal is generated by a second PHY logical unit, and wherein the first amplifier, first multiplexer, second multiplexer, first PHY logical unit, and second PHY logical unit are all included on a same semiconductor die. ### Claim 2 (depends on 1) The apparatus as recited in claim 1, wherein the apparatus is further configured to: generate, on a non-inverting output terminal of the first amplifier, a first output signal based on signals received on the non-inverting input terminal and the inverting input terminal; pass the first output signal through a third capacitor to the first signal path; generate, on an inverting output terminal of the first amplifier, a second output signal based on signals received on the non-inverting input terminal and the inverting input terminal; and pass the second output signal through a fourth capacitor to the second signal path. ### Claim 3 (depends on 2) The apparatus as recited in claim 2, wherein the first amplifier is a fully differential amplifier. ### Claim 4 (depends on 1) The apparatus as recited in claim 1, wherein the apparatus further comprises a second amplifier capacitively coupled to the first signal path and the second signal path. ### Claim 5 (depends on 1) The apparatus as recited in claim 1, wherein the first signal path and second signal path carry bi-directional signals. ### Claim 6 (depends on 1) The apparatus as recited in claim 1, wherein the first signal path and second signal path carry uni-directional signals. ### Claim 7 (depends on 1) The apparatus as recited in claim 1, wherein the first capacitor is a same size as the second capacitor, and wherein the third capacitor is a same size as the fourth capacitor. ### Claim 8 A method comprising: selecting, by a first multiplexor, which one of a first plurality of signal paths is connected to a first signal path, and selecting, by a second multiplexer, which one of a second plurality of signal paths is connected to a second signal path, wherein each of the first signal path and second signal path is connected to a pad that is connected to a USB connector, wherein a first signal received by the first multiplexer is compliant with a universal serial bus protocol, and wherein a second signal received by the first multiplexer is compliant with a DisplayPort protocol; receiving, on a first signal path, a first signal component of a differential signal; passing the first signal component through a first capacitor to a non-inverting input terminal of a first amplifier; receiving, on a second signal path, a second signal component of the differential signal; passing the second signal component through a second capacitor to an inverting input terminal of the first amplifier; and wherein the first signal is generated by a first physical layer (PHY) logical unit, wherein the second signal is generated by a second PHY logical unit, and wherein the first amplifier, first multiplexer, second multiplexer, first PHY logical unit, and second PHY logical unit are all included on a same semiconductor die. ### Claim 9 (depends on 8) The method as recited in claim 8, further comprising: generating, on a non-inverting output terminal of the first amplifier, a first output signal based on signals received on the non-inverting input terminal and the inverting input terminal; passing the first output signal through a third capacitor to the first signal path; generating, on an inverting output terminal of the first amplifier, a second output signal based on signals received on the non-inverting input terminal and the inverting input terminal; and passing the second output signal through a fourth capacitor to the second signal path. ### Claim 10 (depends on 9) The method as recited in claim 9, wherein the first amplifier is a fully differential amplifier. ### Claim 11 (depends on 8) The method as recited in claim 8, further comprising capacitively coupling a second amplifier to the first signal path and the second signal path. ### Claim 12 (depends on 8) The method as recited in claim 8, wherein the first signal path and second signal path carry bi-directional signals. ### Claim 13 (depends on 8) The method as recited in claim 8, wherein the first signal path and second signal path carry uni-directional signals. ### Claim 14 (depends on 8) The method as recited in claim 8, wherein the first capacitor is a same size as the second capacitor, and wherein the third capacitor is a same size as the fourth capacitor. ### Claim 15 A circuit comprising: an amplifier; a first capacitor coupled between a first signal path and a first input terminal of the amplifier; and a second capacitor coupled between the first signal path and a first output terminal of the amplifier; wherein the first signal is generated by a first physical layer (PHY) logical unit, wherein the second signal is generated by a second PHY logical unit, and wherein the amplifier, first multiplexer, second multiplexer, first PHY logical unit, and second PHY logical unit are all included on a same semiconductor die; wherein the circuit further comprises a first multiplexer coupled to the first signal path and a second multiplexer coupled to the second signal path, wherein the first multiplexer is configured to select which one of a first plurality of signal paths is connected to the first signal path, and wherein the second multiplexer is configured to select which one of a second plurality of signal paths is connected to the second signal path; wherein a first signal received by the first multiplexer is compliant with a first protocol, wherein a second signal received by the first multiplexer is compliant with a second protocol, and wherein the second protocol is different from the first protocol, wherein the first protocol is universal serial bus (USB), wherein the second protocol is DisplayPort, and wherein the first signal path and the second signal path are coupled to pads which are connected to a USB type-C connector. ### Claim 16 (depends on 15) The circuit as recited in claim 15, wherein the first input terminal of the amplifier is a non-inverting input terminal, wherein the first output terminal of the amplifier is a non-inverting output terminal. ### Claim 17 (depends on 16) The circuit as recited in claim 16, wherein the circuit further comprises: a third capacitor coupled between a second signal path and a second input terminal of the amplifier; and a fourth capacitor coupled between the second signal path and a second output terminal of the amplifier. ### Claim 18 (depends on 17) The circuit as recited in claim 17, wherein the second input terminal of the amplifier is an inverting input terminal, wherein the second output terminal of the amplifier is an inverting output terminal. ### Claim 19 (depends on 17) The circuit as recited in claim 17, wherein the first and second signal paths carry a differential signal. ### Claim 20 (depends on 17) The circuit as recited in claim 17, wherein the amplifier is a fully differential amplifier.