# US 10,122,382 B2 · VSS LDPC decoder with improved throughput for hard decoding

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- Number: US 10,122,382 B2
- Document ID: US10122382B2
- Status: Granted
- Kind: B2
- Application number: 15/269,686
- Filed: 2016-09-19
- Published: 2017-03-23
- Granted: 2018-11-06
- Earliest claimed: 2015-09-18
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Abhiram Prabhakar; Johnson Yen; Ngok Ying Chu
- Web page: https://patentgrep.com/patent/US10122382B2

## CPC

- H03M 13/1108: {Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping}
- G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)}
- H03M 13/1111: {Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms}
- H03M 13/1122: {storing only the first and second minimum values per check node}
- H03M 13/2906: {using block codes (H03M13/2957 takes precedence)}
- H03M 13/3707: {Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code}
- H03M 13/3723: {using means or methods for the initialisation of the decoder}
- H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Memory systems may include a memory storage, a pre-processing checksum unit suitable for, during a first decoding iteration, receiving hard read data including channel input (Lch) sign values, and computing a checksum of the Lch sign values as a checksum_pre value, and a low-density parity-check (LDPC) decoder including an Lch memory and a checksum update unit, the LDPC decoder suitable for, during the first decoding iteration, storing the Lch sign values in the Lch memory of the LDPC decoder, receiving, with the checksum update unit, the checksum_pre value, and decoding a codeword in at least a second decoding iteration based at least in part on the checksum_pre value computed and received being a parity check on the hard read performed in the first decoding iteration.

## Claims

### Claim 1

A memory system, comprising:
a memory device; and
a processor in communication with, and configured to control, the memory device, wherein the memory device includes:
a memory storage; and
a read processor coupled with the memory storage, wherein the read processor includes a pre-processing checksum unit and a low-density parity-check (LDPC) decoder that share registers and memory,
the pre-processing checksum unit configured to, during a first decoding iteration:
receive hard read data including channel input (Lch) sign values, wherein the hard read data corresponds to data read from the memory storage;
compute a checksum of the Lch sign values and conduct a parity check, as a checksum_pre value; and
output the checksum_pre value to the LDPC decoder;
the LDPC decoder including an Lch memory and a checksum update unit, the LDPC decoder configured to,
during the first decoding iteration:
store the checksum_pre value received from the pre-processing checksum unit in the Lch memory of the LDPC decoder;
receive, by the checksum update unit, the checksum_pre value; and
pipeline the checksum_pre value for a second decoding iteration, wherein the LDPC decoder does not perform error correction during the first decoding iteration; and
in at least the second decoding iteration,
decode a codeword, using the registers and memory shared with the pre-processing checksum unit, based at least in part on the computed and received checksum_pre value, which includes the parity check on the hard read data operations performed by the pre-processing checksum unit in the first decoding iteration; and
update the checksum value, using the checksum update unit, for a next decoding iteration when the second decoding iteration fails; and
return the decoded codeword when the second decoding iteration is successful.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the LDPC decoder further includes a check node update (CNU) unit configured to store the Lch sign values stored in the Lch memory as a sgn_mem value during the second decoding iteration.

### Claim 3 (depends on 1)

The memory system of claim 1, wherein the LDPC decoder further includes a check node update (CNU) unit configured to receive the checksum_pre value during the first decoding iteration and store the checksum_pre value as an all_sgn value.

### Claim 4 (depends on 1)

The memory system of claim 1, wherein the LDPC decoder comprises a min-sum LDPC decoder.

### Claim 5 (depends on 1)

The memory system of claim 1, wherein the LDPC decoder further includes a check node update (CNU) unit configured to initialize a minimum read value field and a minimum read value location field at the beginning of the second decoding iteration.

### Claim 6 (depends on 1)

The memory system of claim 1, wherein the LDPC decoder is available for decoding from the second decoding iteration to the final decoding iteration.

### Claim 7

A method, comprising:
receiving, with a pre-processing checksum unit of a read processor of a memory device, hard read data including channel input Lch sign values, wherein the hard read data corresponds to data read from a memory storage of the memory device;
computing, using the pre-processing checksum unit, a checksum of the Lch sign values and conducting a parity check, as a checksum_pre value;
outputting the checksum_pre value to a low-density parity-check (LDPC) decoder of the read processor;
during a first decoding iteration:
storing, by the LDPC decoder, the checksum_pre value received from the pre-processing checksum unit in a Lch memory of the LDPC decoder;
receiving, by a checksum update unit of the LDPC decoder, the checksum_pre value; and
pipelining, by the LDPC decoder, the checksum_pre value for a second decoding iteration, wherein the LDPC decoder does not perform error correction during the first decoding iteration; and
in at least the second decoding iteration,
decoding, using the LDPC decoder and registers and memory shared by the LDPC decoder and the pre-processing checksum unit, a codeword based at least in part on the computed and received checksum_pre value, which includes the parity check on the hard read operations performed by the pre-processing checksum unit in the first decoding iteration; and
update the checksum value, using the checksum update unit, for a next decoding iteration when the second decoding iteration fails; and
returning the decoded codeword when the second decoding iteration is successful.

### Claim 8 (depends on 7)

The method of claim 7, further comprising storing, with a check node update unit of the LDPC decoder, the Lch sign values stored in the Lch memory as a sgn_mem value during the second decoding iteration.

### Claim 9 (depends on 7)

The method of claim 7, further comprising receiving, with a check node update unit of the LDPC decoder, the checksum_pre value during the first decoding iteration and storing the checksum_pre value as an all_sgn value.

### Claim 10 (depends on 7)

The method of claim 7, wherein the LDPC decoder comprises a min-sum LDPC decoder.

### Claim 11 (depends on 7)

The method of claim 7, further comprising initializing, with a check node update unit of the LDPC decoder, a minimum read value field and a minimum read value location field at the beginning of the second decoding iteration.

### Claim 12 (depends on 7)

The method of claim 7, wherein the LDPC decoder is available for decoding from the second decoding iteration to the final decoding iteration.

### Claim 13

A memory device, comprising:
a memory storage; and
a read processor coupled with the memory storage, wherein the read processor includes a pre-processing checksum unit and a low-density parity-check (LDPC) decoder that share registers and memory, the pre-processing checksum unit configured to, during a first decoding iteration:
receive hard read data including channel input (Lch) sign values, wherein the hard read data corresponds to data read from the memory storage;
compute a checksum of the Lch sign values and conduct a parity check, as a checksum_pre value; and
output the checksum_pre value to the LDPC decoder;
the LDPC decoder including an Lch memory and a checksum update unit, the LDPC decoder configured to,
during the first decoding iteration:
store the checksum_pre value received from the pre-processing checksum unit in the Lch memory of the LDPC decoder;
receive, by the checksum update unit, the checksum_pre value;
pipeline the checksum_pre value for a second decoding iteration, wherein the LDPC decoder does not perform error correction during the first decoding iteration; and
in at least the second decoding iteration,
decode a codeword, using the registers and memory shared with the pre-processing checksum unit, based at least in part on the computed and received checksum_pre value, which includes the parity check on the hard read data operations performed by the pre-processing checksum unit in the first decoding iteration; and
update the checksum value, using the checksum update unit, for a next decoding iteration when the second decoding iteration fails; and
return the decoded codeword when the second decoding iteration is successful.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein the LDPC decoder further includes a check node update (CNU) unit configured to store the Lch sign values stored in the Lch memory as a sgn_mem value during the second decoding iteration.

### Claim 15 (depends on 13)

The memory device of claim 13, wherein the LDPC decoder further includes a check node update (CNU) unit configured to receive the checksum_pre value during the first decoding iteration and store the checksum_pre value as an all_sgn value.

### Claim 16 (depends on 13)

The memory device of claim 13, wherein the LDPC decoder comprises a min-sum LDPC decoder.

### Claim 17 (depends on 13)

The memory device of claim 13, wherein the LDPC decoder further includes a check node update (CNU) unit configured to initialize a minimum read value field and a minimum read value location field at the beginning of the second decoding iteration.

### Claim 18 (depends on 13)

The memory device of claim 13, wherein the LDPC decoder is available for decoding from the second decoding iteration to the final decoding iteration.