# US 10,122,378 B2 · Digital-to-time converter and operating method thereof

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- Number: US 10,122,378 B2
- Document ID: US10122378B2
- Status: Granted
- Kind: B2
- Application number: 15/869,854
- Filed: 2018-01-12
- Published: 2018-09-20
- Granted: 2018-11-06
- Earliest claimed: 2017-03-16
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Nam-seog Kim
- Web page: https://patentgrep.com/patent/US10122378B2

## CPC

- H03M 1/825: {by comparing the input signal with a digital ramp signal}
- G04F 10/005: {Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60)}
- H03F 3/2175: {using analogue-digital or digital-analogue conversion (H03F3/2173 takes precedence)}
- H03K 5/131: Digitally controlled
- H03K 5/135: by the use of time reference signals, e.g. clock signals
- H03L 7/097: using a comparator for comparing the voltages obtained from two frequency to voltage converters
- H03L 7/1976: {using a phase accumulator for controlling the counter or frequency divider}
- H03M 1/68: with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
- H03M 1/785: {using resistors, i.e. R-2R ladders}
- H03L 2207/50: All digital phase-locked loop
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G04F: TIME-INTERVAL MEASURING (measuring pulse characteristics G01R, e.g. G01R29/02; in radar or like systems G01S)
- H03F: AMPLIFIERS
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A digital-to-time converter includes: a digital-to-analog converter configured to generate a precharge voltage corresponding to a value of a digital code; a ramp generator configured to precharge a capacitor connected to a first node based on the precharge voltage, and to charge or discharge the capacitor based on a reference current provided from a current source in response to a transition of an input clock signal to generate a ramp voltage in the first node; and a comparator configured to generate an output clock signal based on the ramp voltage, wherein the ramp generator includes: a first switching circuit configured to provide a first current path between a second node connected to the current source and the first node; and a second switching circuit configured to provide a second current path from a power supply voltage source to the second node.

## Claims

### Claim 1

A digital-to-time converter comprising:
a digital-to-analog converter configured to generate a precharge voltage corresponding to a value of a digital code;
a ramp generator including a first switching circuit configured to provide a first current path between a first node connected to a capacitor and a second node connected to a current source, and
a second switching circuit configured to provide a second current path from a power supply voltage source to the second node,
the ramp generator configured to,
precharge the capacitor connected to the first node based on the precharge voltage, and
charge or discharge the capacitor based on a reference current provided from the current source in response to a transition of an input clock signal to generate a ramp voltage in the first node; and
a comparator configured to generate an output clock signal based on the ramp voltage.

### Claim 2 (depends on 1)

The digital-to-time converter of claim 1, wherein
the digital-to-analog converter is further configured to vary start levels of the ramp voltage by varying the precharge voltage based on the value of the digital code; and
the ramp generator is further configured to maintain a constant slope of the ramp voltage.

### Claim 3 (depends on 1)

The digital-to-time converter of claim 1, wherein the ramp generator is further configured to:
turn on the second switching circuit prior to the first switching circuit to set a voltage level of the second node such that the current source generates the reference current.

### Claim 4 (depends on 1)

The digital-to-time converter of claim 1, wherein
the first switching circuit comprises a first transistor connected between the first node and the second node; and
the second switching circuit comprises a second transistor connected between the power supply voltage source and the second node.

### Claim 5 (depends on 4)

The digital-to-time converter of claim 4, wherein
the first switching circuit further comprises a first switching control circuit configured to provide a first turn-on voltage to a gate of the first transistor in response to a delay clock signal which causes a delay of the input clock signal; and
the second switching circuit further comprises a second switching control circuit configured to provide the first turn-on voltage to a gate of the second transistor in response to the input clock signal.

### Claim 6 (depends on 5)

The digital-to-time converter of claim 5, wherein
the second switching control circuit has the same structure as the first switching control circuit.

### Claim 7 (depends on 6)

The digital-to-time converter of claim 6, wherein,
when the first transistor and the second transistor are turned on in response to the first turn-on voltage, the first transistor and the second transistor operate in a saturation region.

### Claim 8 (depends on 4)

The digital-to-time converter of claim 4, wherein
the first switching circuit further comprises a first switching control circuit configured to provide a first turn-on voltage to a gate of the first transistor in response to a delay clock signal which causes delay of the input clock signal;
the second switching circuit further comprises a second switching control circuit configured to provide a second turn-on voltage to a gate of the second transistor in response to the input clock signal; and
the ramp generator further comprises an amplifier configured to,
amplify a difference between a voltage level of the second node and a voltage level of a control voltage, and
output the amplified difference as the second turn-on voltage such that the voltage level of the second node is equal to the voltage level of the control voltage.

### Claim 9 (depends on 1)

The digital-to-time converter of claim 1, wherein
the DAC comprises an R-2R resistor ladder network.

### Claim 10 (depends on 1)

The digital-to-time converter of claim 1, wherein
the digital code comprises a plurality of bits; and
the digital-to-analog converter is further configured to increase a voltage level of the precharge voltage based on an increase in values of the plurality of bits of the digital code.

### Claim 11

A digital-to-time converter comprising:
a first delay cell configured to generate a first clock signal based on at least one upper bit of a digital code, the first clock signal causing a delay of an input clock signal by a first delay amount; and
a second delay cell configured to generate a second clock signal based on at least one lower bit of the digital code, the second clock signal causing delay of the first clock signal by a second delay amount, wherein
the first delay cell comprises,
a first digital-to-analog converter configured to generate a precharge voltage corresponding to a value of the at least one upper bit;
a first ramp voltage generator configured to,
generate a first ramp voltage whose voltage level changes from a voltage level of the precharge voltage to a first slope based on the precharge voltage, and
output the first ramp voltage through a first output node; and
a first comparator configured to
generate the first clock signal based on a voltage level of the first ramp voltage and a voltage level of a first reference voltage.

### Claim 12 (depends on 11)

The digital-to-time converter of claim 11, wherein the second delay amount is based on a difference between a maximum delay amount and a minimum delay amount that is equal to a unit delay amount of the first delay cell.

### Claim 13 (depends on 11)

The digital-to-time converter of claim 11, wherein the first ramp voltage generator comprises:
a precharge circuit configured to precharge a capacitor connected to the first output node based on the precharge voltage;
a current source configured to discharge a first reference current from the capacitor after the capacitor is precharged;
a first transistor connected between the first output node and a second node that is an input node of the current source and turned on in response to a delay clock signal which causes a delay of the input clock signal to provide a discharge path of the first reference current; and
a second transistor connected between a power supply voltage source and the second node and turned on in response to the input clock signal to set a voltage level of the second node before the first transistor is turned on.

### Claim 14 (depends on 11)

The digital-to-time converter of claim 11, wherein the second delay cell comprises:
a second digital-to-analog converter configured to generate a second voltage based on the at least one lower bit;
a second ramp voltage generator configured to,
receive the first clock signal,
generate a second ramp voltage whose voltage level changes from a level of the second voltage to a second slope based on the second voltage, and
output the second ramp voltage through a second output node; and
a second comparator configured to generate the second clock signal based on a voltage level of the second ramp voltage and a level of a second reference voltage.

### Claim 15 (depends on 14)

The digital-to-time converter of claim 14, wherein
the second slope is greater than the first slope.

### Claim 16 (depends on 11)

The digital-to-time converter of claim 11, wherein the second delay cell comprises:
a second ramp generator configured to generate a second ramp voltage whose level is reduced from a level of a power supply voltage source when the first clock signal transitions, wherein
the second ramp generator comprises,
a variable capacitor configured to store variable capacitance corresponding to a thermometer code according to the least one lower bit;
a current source configured to discharge a second reference current from the variable capacitor; and
a switching circuit configured to,
precharge the variable capacitor based on the power supply voltage source if the first clock signal is at a first level, and
connect the variable capacitor and the current source when the first clock signal transitions from the first level to a second level.

### Claim 17 (depends on 11)

A digital phase-locked loop circuit comprising the digital-to-time converter of claim 11.

### Claim 18

A method of operating a digital-to-time converter, the method comprising:
generating, by a first delay cell, a first clock signal which causes a delay of an input clock signal by a first delay amount based on at least one upper bit of a digital code; and
generating, by a second delay cell, a second clock signal which causes a delay of the first clock signal by a second delay amount based on at least one lower bit of the digital code, wherein
the generating of the first clock signal comprises,
precharging a first load capacitor provided in the first delay cell based on a precharge voltage corresponding to a value of the at least one upper bit,
setting a voltage level of a second node connected to a first current source such that the first current source generates a reference current, and
discharging a constant current based on the reference current from the first load capacitor.

### Claim 19 (depends on 18)

The method of claim 18, wherein the setting of the voltage level of the second node comprises turning on a switch connected to the second node and a power supply voltage source in response to the input clock signal.

### Claim 20 (depends on 18)

The method of claim 18, wherein the generating of the second clock signal comprises:
precharging a second load capacitor whose capacity varies according to a value of the at least one lower bit based on a power supply voltage; and
discharging a second reference current provided from a second current source from the second load capacitor.