# US 10,122,377 B2 · Comparator, circuit device, physical quantity sensor, electronic device, and vehicle

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- Number: US 10,122,377 B2
- Document ID: US10122377B2
- Status: Granted
- Kind: B2
- Application number: 15/848,269
- Filed: 2017-12-20
- Published: 2018-04-26
- Granted: 2018-11-06
- Earliest claimed: 2016-07-25
- Assignees: Seiko Epson Corporation
- Applicants: Seiko Epson Corporation
- Inventors: Hideo Haneda
- Web page: https://patentgrep.com/patent/US10122377B2

## CPC

- H03M 1/50: with intermediate conversion to time interval (H03M1/64 takes precedence)
- H03F 3/45475: {using IC blocks as the active amplifying circuit}
- H03K 5/249: {using clock signals}
- H03K 9/08: of duration- or width-mudulated pulses {or of duty-cycle modulated pulses}
- H03M 1/1245: {Details of sampling arrangements or methods}
- H03M 1/46: with digital/analogue converter for supplying reference values to converter
- H03M 1/56: Input signal compared with linear ramp
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03F: AMPLIFIERS
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A comparator includes a first voltage-time conversion circuit, a second voltage-time conversion circuit, and a determination circuit. A first delay unit includes a first primary conductivity type transistor of which current is controlled based on a first input signal, a first secondary conductivity type transistor of which current is controlled based on a second input signal, and a first delay buffer provided between the transistors. A second delay unit includes a second primary conductivity type transistor of which current is controlled based on a second input signal, a second secondary conductivity type transistor of which current is controlled based on a first input signal, and a second delay buffer provided between the transistors.

## Claims

### Claim 1

A comparator comprising:
a first voltage-time conversion circuit which includes a first delay circuit, the first delay circuit being configured to receive a first input signal and a second input signal;
a second voltage-time conversion circuit which includes a second delay circuit, the second delay circuit being configured to receive the first input signal and the second input signal; and
a determination circuit communicating with the first and second voltage-time conversion circuits, the determination circuit being configured to determine a magnitude relation of the first input signal and the second input signal, based on an output signal of the first voltage-time conversion circuit and an output signal of the second voltage-time conversion circuit,
wherein the first delay circuit includes a first delay unit, the first delay unit including:
a first primary conductivity type transistor, a current of the first primary conductivity type transistor being controlled based on the first input signal,
a first secondary conductivity type transistor, a current of the first secondary conductivity type transistor being controlled based on the second input signal, and
a first delay buffer circuit connected to the first primary conductivity type transistor and the first secondary conductivity type transistor, the first delay buffer circuit being configured to delay an input signal received by the first delay unit and generate a first delayed output signal based on the first input signal and the second input signal, and
wherein the second delay circuit includes a second delay unit, the second delay unit including:
a second primary conductivity type transistor, a current of the second primary conductivity type transistor being controlled based on the second input signal,
a second secondary conductivity type transistor, a current of the second secondary conductivity type transistor being controlled based on the first input signal, and
a second delay buffer circuit connected to the second primary conductivity type transistor and the second secondary conductivity type transistor, the second delay buffer circuit being configured to delay an input signal received by the second delay unit and generate a second delayed output signal based on the first input signal and the second input signal.

### Claim 2 (depends on 1)

The comparator according to claim 1,
wherein the first delay circuit includes a plurality of the first delay units connected in series; and
the second delay circuit includes a plurality of the second delay units connected in series.

### Claim 3 (depends on 2)

The comparator according to claim 2,
wherein in the first delay circuit, the first primary conductivity type transistor and the first secondary conductivity type transistor are shared between at least two delay units of the plurality of delay units, and
wherein in the second delay circuit, the second primary conductivity type transistor and the second secondary conductivity type transistor are shared between at least two delay units of the plurality of delay units.

### Claim 4 (depends on 1)

The comparator according to claim 1,
wherein in a case where a determination result of the determination circuit is confirmed, power supply voltages to be supplied to the first delay buffer circuit and the second delay buffer circuit are set to a predetermined voltage.

### Claim 5 (depends on 1)

The comparator according to claim 1,
wherein a delay time of the first delay buffer circuit is controlled based on a current flowing through any one of the first primary conductivity type transistor and the first secondary conductivity type transistor, and
wherein a delay time of the second delay buffer circuit is controlled based on a current flowing through any one of the second primary conductivity type transistor and the second secondary conductivity type transistor.

### Claim 6 (depends on 1)

The comparator according to claim 1,
wherein the first voltage-time conversion circuit further includes
a first input signal generation circuit that generates the input signal received by the first delay circuit, and
a first latch circuit configured to operate based on an output signal of the first delay circuit, and
wherein the second voltage-time conversion circuit further includes
a second input signal generation circuit that generates the input signal received by the second delay circuit, and
a second latch circuit configured to operate based on an output signal of the second delay circuit.

### Claim 7 (depends on 6)

The comparator according to claim 6,
wherein the first input signal generation circuit is configured to change the input signal input to the first delay unit from a first logic level to a second logic level, and to change the input signal input to the first delay unit from the second logic level to the first logic level, in a case where the output signal of the first delay circuit changes from the first logic level to the second logic level,
wherein the first latch circuit is configured to change the output signal of the first voltage-time conversion circuit from the second logic level to the first logic level, in a case where the output signal of the first delay circuit changes from the second logic level to the first logic level,
wherein the second input signal generation circuit is configured to change the input signal input to the second delay unit from the first logic level to the second logic level, and to change the input signal input to the second delay unit from the second logic level to the first logic level, in a case where the output signal of the second delay circuit changes from the first logic level to the second logic level, and
wherein the second latch circuit is configured to change the output signal of the second voltage-time conversion circuit from the second logic level to the first logic level, in a case where the output signal of the second delay circuit changes from the second logic level to the first logic level.

### Claim 8 (depends on 1)

The comparator according to claim 1,
wherein the first voltage-time conversion circuit further includes a first measurement circuit that measures a number of pulses of an output signal from the first delay circuit,
wherein the output signal of the first voltage-time conversion circuit is generated based on a measurement result of the first measurement circuit,
wherein the second voltage-time conversion circuit further includes a second measurement circuit that measures a number of pulses of an output signal from the second delay circuit, and
wherein the output signal of the second voltage-time conversion circuit is generated based on a measurement result of the second measurement circuit.

### Claim 9 (depends on 8)

The comparator according to claim 8,
wherein the first voltage-time conversion circuit further includes a first ring oscillator which includes the first delay circuit, and in which the output signal from the first delay circuit is fed back to the input signal received by the first delay unit, and
wherein the second voltage-time conversion circuit further includes a second ring oscillator which includes the second delay circuit, and in which the output signal from the second delay circuit is fed back to the input signal received by the second delay unit.

### Claim 10 (depends on 9)

The comparator according to claim 9,
wherein the first voltage-time conversion circuit further includes a third input signal generation circuit that receives an enable signal and a signal based on the output signal from the first delay circuit, and generates the input signal received by the first delay unit, and
wherein the second voltage-time conversion circuit further includes a fourth input signal generation circuit that receives the enable signal and a signal based on the output signal of the second delay circuit, and generates the input signal received by the second delay unit.

### Claim 11 (depends on 1)

A circuit device comprising the comparator according to claim 1.

### Claim 12 (depends on 2)

A circuit device comprising the comparator according to claim 2.

### Claim 13 (depends on 3)

A circuit device comprising the comparator according to claim 3.

### Claim 14 (depends on 4)

A circuit device comprising the comparator according to claim 4.

### Claim 15 (depends on 11)

A physical quantity sensor comprising the circuit device according to claim 11.

### Claim 16 (depends on 12)

A physical quantity sensor comprising the circuit device according to claim 12.

### Claim 17 (depends on 11)

An electronic device comprising the circuit device according to claim 11.

### Claim 18 (depends on 12)

An electronic device comprising the circuit device according to claim 12.

### Claim 19 (depends on 11)

A vehicle comprising the circuit device according to claim 11.

### Claim 20 (depends on 12)

A vehicle comprising the circuit device according to claim 12.