# US 10,122,375 B2 · Time-based delay line analog-to-digital converter with variable resolution

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- Number: US 10,122,375 B2
- Document ID: US10122375B2
- Status: Granted
- Kind: B2
- Application number: 15/915,796
- Filed: 2018-03-08
- Published: 2018-07-12
- Granted: 2018-11-06
- Earliest claimed: 2016-04-12
- Assignees: Microchip Technology Incorporated
- Applicants: Microchip Technology Incorporated
- Inventors: Bryan Kris; Neil Deutscher; Thomas S. Spohrer
- Web page: https://patentgrep.com/patent/US10122375B2

## CPC

- H03M 1/34: Analogue value compared with reference values (H03M1/48 takes precedence)
- H02M 3/156: with automatic control of output voltage or current, e.g. switching regulators
- H03K 5/131: Digitally controlled
- H03K 5/14: by the use of delay lines (H03K5/133 takes precedence)
- H03M 1/007: {among different resolutions}
- H03M 1/1009: {Calibration}
- H03M 1/1028: {at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error (gain setting for range control H03M1/18)}
- H03M 1/1057: {by trimming, i.e. by individually adjusting at least part of the quantisation value generators or stages to their nominal values}
- H03M 1/1071: {Measuring or testing}
- H03M 1/18: Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
- H03M 1/38: sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14)
- H03K 2005/00058: {controlled by a digital setting}
- H03M 1/502: {using tapped delay lines}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.

## Claims

### Claim 1

A differential digital delay line analog-to-digital converter (ADC), comprising:
differential digital delay lines comprising a plurality of series coupled delay cells, wherein a delay time of a first delay line is related to a first voltage at an input of the ADC and a delay time of a second delay line is related to a second voltage at the input of the ADC;
a first bypass circuit communicatively coupled at a predefined node location in the series coupled delay cells;
a plurality of storage circuits each coupled with the series coupled delay cells;
a converter circuit coupled with the plurality of storage circuits configured to convert data from the storage circuits into an output value of the ADC; and
a plurality of logic circuits configured to select data from the storage circuits depending on a selected resolution of the differential digital delay line analog-to-digital converter.

### Claim 2 (depends on 1)

The ADC of claim 1, wherein the first bypass circuit includes a multiplexer.

### Claim 3 (depends on 1)

The ADC of claim 1, wherein the first bypass circuit is placed at a 50% point of the series coupled delay cells.

### Claim 4 (depends on 1)

The ADC of claim 1, further comprising a second bypass circuit located at a 50% point between the first bypass circuit and a delay line end.

### Claim 5 (depends on 4)

The ADC of claim 4, wherein the second bypass circuit is configured to reduce a resolution of the ADC.

### Claim 6 (depends on 1)

The ADC of claim 1, wherein the first bypass circuit is configured to selectively bypass part of the differential digital delay lines according to the selected resolution.

### Claim 7 (depends on 1)

The ADC of claim 1, further comprising additional bypass circuits, wherein each of the first bypass circuit and the additional bypass circuits is associated with a bit of resolution of the ADC.

### Claim 8

A microcontroller comprising:
a processor core;
a memory; and
a differential digital delay line analog-to-digital converter (ADC), comprising:
differential digital delay lines comprising a plurality of series coupled delay cells, wherein a delay time of a first delay line is related to a first voltage at an input of the ADC and a delay time of a second delay line is related to a second voltage at the input of the ADC;
a first bypass circuit communicatively coupled at a predefined node location in the series coupled delay cells;
a plurality of storage circuits each coupled with the series coupled delay cells;
a converter circuit coupled with the plurality of storage circuits configured to convert data from the storage circuits into an output value of the ADC; and
a plurality of logic circuits configured to select data from the storage circuits depending on a selected resolution of the differential digital delay line analog-to-digital converter.

### Claim 9 (depends on 8)

The processor of claim 8, wherein the first bypass circuit includes a multiplexer.

### Claim 10 (depends on 8)

The processor of claim 8, wherein the first bypass circuit is placed at a 50% point of the series coupled delay cells.

### Claim 11 (depends on 8)

The processor of claim 8, further comprising a second bypass circuit located at a 50% point between the first bypass circuit and a delay line end.

### Claim 12 (depends on 11)

The processor of claim 11, wherein the second bypass circuit is configured to reduce a resolution of the ADC.

### Claim 13 (depends on 8)

The processor of claim 8, wherein the first bypass circuit is configured to selectively bypass part of the differential digital delay lines according to the selected resolution.

### Claim 14 (depends on 8)

The processor of claim 8, further comprising additional bypass circuits, wherein each of the first bypass circuit and the additional bypass circuits is associated with a bit of resolution of the ADC.

### Claim 15

A method of converting an analog signal to a digital value, comprising:
applying a first voltage to a differential digital delay line analog-to-digital converter (ADC);
applying a second voltage to the ADC;
passing signals through a plurality of series coupled delay cells in the ADC, wherein a delay time of a first delay line is related to the first voltage and a delay time of a second delay line is related to the second voltage;
storing values from the series coupled delay cells in a plurality of storage circuits;
converting, with a converter circuit, data from the storage circuits into an output value of the ADC;
passing the signals through a first bypass circuit communicatively coupled at a predefined node location in the series coupled delay cells; and
selecting data from the storage circuits depending on a selected resolution of the ADC.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first bypass circuit is placed at a 50% point of the series coupled delay cells.

### Claim 17 (depends on 15)

The method of claim 15, further comprising passing the signals through a second bypass circuit located at a 50% point between the first bypass circuit and a delay line end.

### Claim 18 (depends on 17)

The method of claim 17, further comprising reducing resolution of the ADC by passing the signals through the second bypass circuit located at the 50% point between the first bypass circuit and a delay line end.

### Claim 19 (depends on 18)

The method of claim 18, further comprising selectively bypassing part of the differential digital delay lines according to the selected resolution.

### Claim 20 (depends on 19)

The method of claim 19, further comprising passing the signals through additional bypass circuits, wherein each of the first bypass circuit and the additional bypass circuits is associated with a bit of resolution of the ADC.