# US 10,122,371 B2 · Reconfigurable calculation unit with atomic computation units and control inputs

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- Number: US 10,122,371 B2
- Document ID: US10122371B2
- Status: Granted
- Kind: B2
- Application number: 15/816,408
- Filed: 2017-11-17
- Published: 2018-03-22
- Granted: 2018-11-06
- Earliest claimed: 2006-09-15
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Roman Staszewski; Robert B. Staszewski; Fuqiang Shi
- Web page: https://patentgrep.com/patent/US10122371B2

## CPC

- H03L 7/0992: {comprising a counter or a frequency divider}
- G06F 7/605: {Additive or subtractive mixing of two pulse rates into one (beat-frequency oscillators H03B21/00; input circuits of electric counters, e.g. up-down counters H03K21/00)}
- G06F 9/30014: {with variable precision}
- G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE}
- G06F 9/30181: {Instruction operation extension or modification}
- G06F 17/10: Complex mathematical operations {(function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544)}
- H03L 7/1974: {for fractional frequency division}
- H03L 7/1976: {using a phase accumulator for controlling the counter or frequency divider}
- H04B 1/04: Circuits
- H04W 56/003: {Arrangements to increase tolerance to errors in transmission or reception timing}
- H03L 2207/50: All digital phase-locked loop
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04B: TRANSMISSION
- H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72)

## Abstract

A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.

## Claims

### Claim 1

A reconfigurable calculation unit comprising:
(a) data inputs Ra and Rb;
(b) data outputs Rd_st and Rd;
(c) atomic computation units having an input connected to the Ra input, multiplexer inputs, and an output coupled to the Rd_st data output;
(d) a first storage element having an input connected to the Ra data input and an S_d output, and a second storage element having an input connected to the Rd_st data output and an output connected to the Rd output;
(e) a frequency command word register having an FCW output and a phase error register having a PHE output;
(f) multiplexers having inputs coupled to the Rb data input, the S_d output, the Rd data output, the FCW output, and the PHE output, and having outputs selectively coupled to the multiplexer inputs of the atomic computation units; and
(g) control signal inputs coupled to the atomic computation units, the storage elements, the local registers, and the multiplexers.

### Claim 2 (depends on 1)

The reconfigurable calculation unit of claim 1 in which the atomic computation units include:
a first adder/subtractor having an input connected to the Ra input, an input coupled to the Rb input and the Rd output, and a first output;
a shifter having an input connected to the first output, a shift amount input, and a shift output; and
a second adder/subtractor having an input connected to the shift output, an input selectively coupled to the Rb data input, the Rd output, the FCW output, and the PHE output, and an output connected to the Rd_st output.

### Claim 3 (depends on 1)

The reconfigurable calculation unit of claim 1 in which the atomic computation units include:
a first adder/subtractor having an input selectively coupled to the Ra input, an input selectively coupled to the Rb input and the Rd output through a first multiplexer, and a first output;
a shifter having an input selectively coupled to the first output, a shift amount input, and a shift output; and
a second adder/subtractor having an input connected to the shift output, an input selectively coupled to the Rb data input, the Rd output, the FCW output, and the PHE output through a second multiplexer, and an output connected to the Rd_st output.

### Claim 4 (depends on 1)

The reconfigurable calculation unit of claim 1 in which the atomic computation units include:
a first adder/subtractor having an input selectively coupled to the Ra input, an input selectively coupled to the Rb input and the Rd output through a first multiplexer, and a first output;
a shifter having an input selectively coupled to the first output, a shift amount input, and a shift output; and
a second adder/subtractor having an input connected to the shift output, an input selectively coupled to the Rb data input and the Rd output through the first multiplexer, to the FCW output, and the PHE output through a second multiplexer, and an output connected to the Rd_st output.

### Claim 5 (depends on 1)

The reconfigurable calculation unit of claim 1 in which the first storage element and the second storage element have clock inputs.