# US 10,122,362 B2 · Dynamic biasing circuitry for level-shifter circuitry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,122,362 B2 - Document ID: US10122362B2 - Status: Granted - Kind: B2 - Application number: 15/485,044 - Filed: 2017-04-11 - Published: 2018-10-11 - Granted: 2018-11-06 - Earliest claimed: 2017-04-11 - Assignees: Infineon Technologies Austria AG - Applicants: Infineon Technologies Austria AG - Inventors: Giacomo Cascio; Giuseppe Bernacchia; Adriano Sambucco - Web page: https://patentgrep.com/patent/US10122362B2 ## CPC - H03K 19/018521: {of complementary type, e.g. CMOS} - H03K 17/102: {in field-effect transistor switches} - H03K 17/567: Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT - H03K 17/74: by the use, as active elements, of diodes (by the use of more than one type of semiconductor device H03K17/567; by the use of tunnel diodes H03K17/58; by the use of negative resistance diodes H03K17/70) - H03K 2217/0063: High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load - H03K 2217/0081: Power supply means, e.g. to the switch driver - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract In some examples, a device includes level-shifter circuitry and biasing circuitry including at least four diodes, wherein each diode of the at least four diodes is electrically connected in series. The biasing circuitry further includes push-pull circuitry electrically connected to at least two diodes of the at least four diodes and configured to generate an intermediate voltage signal. The biasing circuitry is configured to deliver a high-side biasing signal to the level-shifter circuitry based on the intermediate voltage signal and a high-side voltage signal from the at least four diodes. The biasing circuitry is further configured to deliver a low-side biasing signal to the level-shifter circuitry based on the intermediate voltage signal and a low-side voltage signal from the at least four diodes. ## Claims ### Claim 1 A device comprising: level-shifter circuitry; and biasing circuitry comprising: at least four diodes, wherein each diode of the at least four diodes is electrically connected in series; and push-pull circuitry electrically connected to at least two diodes of the at least four diodes and configured to generate an intermediate voltage signal, wherein the biasing circuitry is configured to: deliver a high-side biasing signal to the level-shifter circuitry based on the intermediate voltage signal and a high-side voltage signal from the at least four diodes, and deliver a low-side biasing signal to the level-shifter circuitry based on the intermediate voltage signal and a low-side voltage signal from the at least four diodes. ### Claim 2 (depends on 1) The device of claim 1, wherein the biasing circuitry further comprises: a high-side capacitor; and a low-side capacitor, wherein the push-pull circuitry is further configured to deliver the intermediate voltage signal to the high-side capacitor and the low-side capacitor, wherein the biasing circuitry is configured to deliver the high-side biasing signal based on the intermediate voltage signal delivered to the high-side capacitor, and wherein the biasing circuitry is configured to deliver the low-side biasing signal based on the intermediate voltage signal delivered to the low-side capacitor. ### Claim 3 (depends on 2) The device of claim 2, wherein the biasing circuitry further comprises: a high-side filter resistor electrically connected to the at least four diodes and the high-side capacitor; and a low-side filter resistor electrically connected to the at least four diodes and the low-side capacitor, wherein the biasing circuitry is configured to deliver the high-side biasing signal to the level-shifter circuitry based on the high-side voltage signal received from the high-side filter resistor, and wherein the biasing circuitry is configured to deliver the low-side biasing signal to the level-shifter circuitry based on the low-side voltage signal received from the low-side filter resistor. ### Claim 4 (depends on 1) The device of claim 1, wherein the level-shifter circuitry is first level-shifter circuitry, wherein the push-pull circuitry is first push-pull circuitry, wherein the intermediate voltage signal is a first intermediate voltage signal, wherein the high-side biasing signal is a first high-side biasing signal, wherein the low-side biasing signal is a first low-side biasing signal, wherein the high-side voltage signal is a first high-side voltage signal, and wherein the low-side voltage signal is a first low-side voltage signal, the device further comprising second level-shifter circuitry, wherein the biasing circuitry further comprises second push-pull circuitry electrically connected to the at least two diodes of the at least four diodes and configured to generate a second intermediate voltage signal, wherein the biasing circuitry is further configured to: deliver a second high-side biasing signal to the second level-shifter circuitry based on the second intermediate voltage signal and a second high-side voltage signal from the at least four diodes, and deliver a second low-side biasing signal to the second level-shifter circuitry based on the second intermediate voltage signal and a second low-side voltage signal from the at least four diodes. ### Claim 5 (depends on 4) The device of claim 4, further comprising a first high-side capacitor, a first low-side capacitor, a second high-side capacitor, and a second low-side capacitor, wherein the first push-pull circuitry is further configured to deliver the first intermediate voltage signal to the first high-side capacitor and the first low-side capacitor, wherein the biasing circuitry is configured to deliver the first high-side biasing signal based on the first intermediate voltage signal delivered to the first high-side capacitor, wherein the biasing circuitry is configured to deliver the first low-side biasing signal based on the first intermediate voltage signal delivered to the first low-side capacitor, wherein the second push-pull circuitry is further configured to deliver the second intermediate voltage signal to the second high-side capacitor and the second low-side capacitor, wherein the biasing circuitry is configured to deliver the second high-side biasing signal based on the second intermediate voltage signal delivered to the second high-side capacitor, and wherein the biasing circuitry is configured to deliver the second low-side biasing signal based on the second intermediate voltage signal delivered to the second low-side capacitor. ### Claim 6 (depends on 1) The device of claim 1, further comprising floating voltage supply circuitry and low-side voltage supply circuitry, wherein the biasing circuitry further comprises: at least one high-side biasing resistor electrically connected in series between the floating voltage supply circuitry and the at least four diodes; and at least one low-side biasing resistor electrically connected in series between the at least four diodes and the low-side voltage supply circuitry. ### Claim 7 (depends on 6) The device of claim 6, further comprising: auxiliary voltage supply circuitry; a clamping diode; and at least two blocking diodes electrically connected in series between the auxiliary voltage supply circuitry and the floating voltage supply circuitry, wherein the at least two blocking diodes are configured to deliver a voltage signal from the auxiliary voltage supply circuitry to the floating voltage supply circuitry, wherein the push-pull circuitry is further configured to deliver the intermediate voltage signal through the clamping diode to an intermediate node of the at least two blocking diodes. ### Claim 8 (depends on 6) The device of claim 6, wherein the level-shifter circuitry comprises: a first set of switches electrically connected in series between the floating voltage supply circuitry and the low-side voltage supply circuitry, wherein the first set of switches includes first cascode circuitry configured to receive the high-side biasing signal and the low-side biasing signal; and a second set of switches electrically connected in series between the floating voltage supply circuitry and the low-side voltage supply circuitry, wherein the second set of switches includes second cascode circuitry configured to receive the high-side biasing signal and the low-side biasing signal. ### Claim 9 (depends on 8) The device of claim 8, wherein the first cascode circuitry comprises a first high-side switch and a first low-side switch, wherein the second cascode circuitry comprises a second high-side switch and a second low-side switch, wherein a control terminal of the first high-side switch and a control terminal of the second high-side switch are configured to receive the high-side biasing signal, and wherein a control terminal of the first low-side switch and a control terminal of the second low-side switch are configured to receive the low-side biasing signal. ### Claim 10 (depends on 6) The device of claim 6, wherein a voltage difference between the intermediate voltage signal and the low-side voltage supply circuitry is approximately one-half of a voltage difference between the floating voltage supply circuitry and the low-side voltage supply circuitry. ### Claim 11 (depends on 6) The device of claim 6, wherein the biasing circuitry further comprises a bootstrap capacitor electrically connected in parallel with the at least one high-side biasing resistor. ### Claim 12 (depends on 1) The device of claim 1, wherein each diode of the at least four diodes is a diode-connected metal-oxide-semiconductor transistor. ### Claim 13 (depends on 1) The device of claim 1, further comprising: half-bridge circuitry comprising a high-side power switch and a low-side power switch, wherein a switch node is electrically connected between the high-side power switch and the low-side power switch; gate driver circuitry configured to deliver control signals to a control terminal of the high-side power switch based on shifted pulse-width modulated signals received from the level-shifter circuitry. ### Claim 14 A method for biasing level-shifter circuitry, the method comprising: delivering a high-side biasing signal to level-shifter circuitry based on an intermediate voltage signal generated by push-pull circuitry electrically connected to at least four diodes, and further based on a high-side voltage signal from the at least four diodes, wherein each diode of the at least four diodes is electrically connected in series; and delivering a low-side biasing signal to the level-shifter circuitry based on the intermediate voltage signal and a low-side voltage signal from the at least four diodes. ### Claim 15 (depends on 14) The method of claim 14, wherein delivering the high-side biasing signal to the level-shifter circuitry is based on the intermediate voltage signal delivered to a high-side capacitor and further based on the high-side voltage signal received from a high-side filter resistor electrically connected to the at least four diodes and the high-side capacitor, and wherein delivering the low-side biasing signal to the level-shifter circuitry is based on the intermediate voltage signal delivered to a low-side capacitor and further based on the low-side voltage signal received from a low-side filter resistor electrically connected to the at least four diodes and the low-side capacitor. ### Claim 16 (depends on 14) The method of claim 14, wherein the level-shifter circuitry is first level-shifter circuitry, wherein the push-pull circuitry is first push-pull circuitry, wherein the intermediate voltage signal is a first intermediate voltage signal, wherein the high-side biasing signal is a first high-side biasing signal, wherein the low-side biasing signal is a first low-side biasing signal, wherein the high-side voltage signal is a first high-side voltage signal, and wherein the low-side voltage signal is a first low-side voltage signal, the method further comprising: delivering a second high-side biasing signal to second level-shifter circuitry based on a second intermediate voltage signal generated by second push-pull circuitry electrically connected to the at least four diodes, and further based on a second high-side voltage signal from the at least four diodes; and delivering a second low-side biasing signal to the second level-shifter circuitry based on the second intermediate voltage signal and a second low-side voltage signal from the at least four diodes. ### Claim 17 (depends on 14) The method of claim 14, further comprising delivering the intermediate voltage signal through a clamping diode to an intermediate node of at least two blocking diodes, wherein the at least two blocking diodes are electrically connected between auxiliary voltage supply circuitry and floating voltage supply circuitry, and wherein the at least two blocking diodes are configured to deliver a voltage signal to the floating voltage supply circuitry, wherein the floating voltage supply circuitry is electrically connected to the level-shifting circuitry. ### Claim 18 (depends on 14) The method of claim 14, wherein delivering the high-side biasing signal comprises delivering the high-side biasing signal to a first high-side switch of first cascode circuitry of a first set of switches of the level-shifter circuitry and a second high-side switch of second cascode circuitry of a second set of switches of the level-shifter circuitry, wherein delivering the low-side biasing signal comprises delivering the low-side biasing signal to a first low-side switch of the first cascode circuitry and a second low-side switch of the second cascode circuitry. ### Claim 19 A device comprising a single semiconductor die including: half-bridge circuitry comprising a high-side power switch and a low-side power switch, wherein the high-side power switch and the low-side power switch are electrically connected by a switch node; level-shifter circuitry; gate driver circuitry configured to deliver control signals to a control terminal of the high-side power switch based on shifted pulse-width modulated signals received from the level-shifter circuitry; and biasing circuitry comprising: at least four diodes, wherein each diode of the at least four diodes is electrically connected in series; a high-side capacitor and a low-side capacitor; push-pull circuitry electrically connected to at least two diodes of the at least four diodes and configured to deliver an intermediate voltage signal to the high-side capacitor and the low-side capacitor, wherein the biasing circuitry is configured to: deliver a high-side biasing signal to the level-shifter circuitry based on the intermediate voltage signal delivered to the high-side capacitor and further based on a high-side voltage signal from the at least four diodes, and deliver a low-side biasing signal to the level-shifter circuitry based on the intermediate voltage signal delivered to the low-side capacitor and further based on a low-side voltage signal from the at least four diodes. ### Claim 20 (depends on 19) The device of claim 19, wherein the single semiconductor die further includes: floating voltage supply circuitry; auxiliary voltage supply circuitry; at least two blocking diodes electrically connected in series between the auxiliary voltage supply circuitry and the floating voltage supply circuitry, wherein the at least two blocking diodes are configured to deliver a voltage signal from the auxiliary voltage supply circuitry to the floating voltage supply circuitry; and a clamping diode, wherein the push-pull circuitry is further configured to deliver the intermediate voltage signal through the clamping diode to an intermediate node of the at least two blocking diodes.