# US 10,122,359 B2 · Integrated circuit control of anti-series switches > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,122,359 B2 - Document ID: US10122359B2 - Status: Granted - Kind: B2 - Application number: 14/820,597 - Filed: 2015-08-07 - Published: 2017-02-09 - Granted: 2018-11-06 - Earliest claimed: 2015-08-07 - Assignees: Semiconductor Components Industries, LLC - Applicants: Semiconductor Components Industries, LLC - Inventors: Johan Camiel Julia Janssens - Web page: https://patentgrep.com/patent/US10122359B2 ## CPC - H03K 17/687: the devices being field-effect transistors - H03K 17/6874: {in a symmetrical configuration} - H03K 19/1732: {by limitation or reduction of the pin/gate ratio (for data-processing equipment G06F1/22)} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An integrated circuit controls one or more external back-to-back (anti-series) transistor switches with three pins per switch. Two pins couple the switch terminals of the external switch to terminals of an internal anti-series switch. An intermediate source node of the internal switch provides a reference voltage that is representative of the external switch's intermediate source node. A predriver of the integrated circuit drives a gate signal relative to the reference voltage, enabling fast, non-dissipative switching of the external switch. A disclosed method includes coupling switch terminal signals from an external anti-series switch to terminals of an internal anti-series switch; and driving a gate signal to the external anti-series switch relative to a reference voltage of an intermediate node of the internal anti-series switch. ## Claims ### Claim 1 An integrated circuit to control at least one off-chip anti-series switch having two transistors in series between two switch terminals, the transistors having their sources connected at an external intermediate node and their gates connected at a shared gate node, the integrated circuit comprising: a set of integrated circuit pins for coupling on-chip circuitry to off-chip components, the set including: a gate pin that couples to the shared gate node of said at least one off-chip anti-series switch; two terminal pins that couple to the two switch terminals of said at least one off-chip anti-series switch; an on-chip anti-series switch including two integrated transistors between the two terminal pins, the two integrated transistors operating to create an internal reference voltage on an internal intermediate node that connects their sources, the internal reference voltage mirroring a voltage of the external intermediate node without having a direct connection to the external intermediate node; and an on-chip controller with a predriver that drives the gate pin relative to the reference voltage. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the two integrated transistors are matched to each other. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein the two integrated transistors have a shared gate terminal coupled to the gate pin. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein the two integrated transistors have a shared gate node driven by the controller separately from the gate pin. ### Claim 5 (depends on 1) The integrated circuit of claim 1, wherein each of the two integrated transistors have a respective gate driven by a respective gate signal from the controller, wherein the respective gate signals are different from each other. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein a buffered version of the reference voltage serves as local ground for the predriver. ### Claim 7 (depends on 1) The integrated circuit of claim 1, wherein the predriver receives as a local ground a level-shifted version of the reference voltage. ### Claim 8 (depends on 1) The integrated circuit of claim 1, wherein the controller asserts and de-asserts the gate pin based at least in part on voltages of the two terminal pins. ### Claim 9 (depends on 1) The integrated circuit of claim 1, wherein the controller asserts and de-asserts the gate pin based at least in part on the reference voltage. ### Claim 10 (depends on 1) The integrated circuit of claim 1, wherein the two integrated transistors have a lower gate breakdown voltage than the two transistors of the off-chip anti-series switch. ### Claim 11 (depends on 1) The integrated circuit of claim 1, wherein said set of integrated circuit pins is for driving one off-chip anti-series switch, and wherein the integrated circuit comprises multiple such sets of integrated pins, each set for driving a respective off-chip anti-series switch. ### Claim 12 (depends on 11) The integrated circuit of claim 11, wherein the integrated circuit comprises for each set of integrated circuit pins a corresponding internal anti-series switch. ### Claim 13 A method for controlling an external off-chip anti-series switch having an external intermediate node, said controlling employing an integrated circuit that forgoes direct or short-circuit access to the external intermediate node, the method comprising: coupling switch terminal signals from the external anti-series switch to terminals of an internal anti-series switch of the integrated circuit; operating the internal anti-series switch to create, at an internal intermediate node connecting their sources, a reference voltage that mirrors a voltage of the external intermediate node without having a direct connection between the internal intermediate node and the external intermediate node; and driving a gate signal to the external anti-series switch relative to the reference voltage. ### Claim 14 (depends on 13) The method of claim 13, further comprising coupling the gate signal to a shared gate of integrated transistors forming the internal anti-series switch. ### Claim 15 (depends on 13) The method of claim 13, further comprising driving gates of the integrated transistors forming the internal anti-series switch separately from the gate signal to the external anti-series switch. ### Claim 16 (depends on 13) The method of claim 13, further comprising deriving a local ground for a predriver supplying the gate signal from a level-shifted version of the reference voltage. ### Claim 17 (depends on 13) The method of claim 13, further comprising buffering the reference voltage as a local ground for a predriver supplying the gate signal. ### Claim 18 (depends on 13) The method of claim 13, further comprising employing multiple internal anti-series switches to provide reference voltages representing intermediate node voltages of corresponding external anti-series switches. ### Claim 19 (depends on 18) The method of claim 18, wherein each intermediate node for the internal and external anti-series switches is a shared source node. ### Claim 20 (depends on 13) The method of claim 13, wherein said driving includes asserting and de-asserting the gate signal based at least in part on the reference voltage.