# US 10,122,354 B2 · Multi-channel clock distribution circuit and electronic device

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- Number: US 10,122,354 B2
- Document ID: US10122354B2
- Status: Granted
- Kind: B2
- Application number: 15/700,916
- Filed: 2017-09-11
- Published: 2018-03-15
- Granted: 2018-11-06
- Earliest claimed: 2016-09-13
- Assignees: Huawei Technologies Co., Ltd.
- Applicants: Huawei Technologies Co., Ltd.
- Inventors: Jinda Yang; Liren Zhou
- Web page: https://patentgrep.com/patent/US10122354B2

## CPC

- H03K 5/1508: {using a plurality of delay lines}
- H03K 2005/00286: {Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A multi-channel clock distribution circuit and an electronic device includes a power source, a first switch, and at least two clock distribution sub-circuits; each clock distribution sub-circuit includes a second switch, a third switch, and a capacitor; a first end of the capacitor is connected to the power source by using the second switch and is connected to the first end of the first switch by using the third switch, a second end of the capacitor is grounded, and the first end of the capacitor is used as an output end of the clock distribution sub-circuits; and connection and disconnection of the first switch is controlled by a first clock signal, connection and disconnection of the second switch is controlled by a second clock signal, and connection and disconnection of the third switch is controlled by a third clock signal.

## Claims

### Claim 1

A multi-channel clock distribution circuit, comprising:
a power source;
at least two clock distribution sub-circuits electrically connected to the power source; and
a first switch electrically connected to each of the clock distribution sub-circuits,
wherein each clock distribution sub-circuit comprises a second switch, a third switch, and a capacitor,
wherein a respective first end of each of the clock distribution sub-circuits is connected to the power source,
wherein a respective second end of each of the clock distribution sub-circuits is connected to a first end of the first switch,
wherein a second end of the first switch is grounded,
wherein a first end of the capacitor is connected to the power source by using the second switch,
wherein the first end of the capacitor is connected to the first end of the first switch by using the third switch,
wherein a second end of the capacitor is grounded,
wherein the first end of the capacitor is used as an output end of each of the clock distribution sub-circuits,
wherein each connection of the first switch and disconnection of the first switch is controlled by a first clock signal,
wherein each connection of the second switch and disconnection of the second switch is controlled by a second clock signal, and
wherein each connection of the third switch and disconnection of the third switch is controlled by a third clock signal.

### Claim 2 (depends on 1)

The multi-channel clock distribution circuit according to claim 1, wherein each of the first switch, the second switch, and the third switch is a metal oxide semiconductor (MOS) transistor.

### Claim 3 (depends on 2)

The multi-channel clock distribution circuit according to claim 2, further comprising a control signal generation circuit, wherein the second switch comprises a first p-channel metal oxide semiconductor (PMOS) transistor, wherein the first switch comprises a first N-channel metal oxide semiconductor (NMOS) transistor, wherein the third switch comprises a second NMOS transistor, wherein a source of the first PMOS transistor is connected to the power source, wherein a drain of the first PMOS transistor is connected to a drain of the second NMOS transistor, wherein a source of the second NMOS transistor is connected to a drain of the first NMOS transistor, wherein each of a gate of the first PMOS transistor, a gate of the first NMOS transistor, and a gate of the second NMOS transistor are externally connected to the control signal generation circuit, wherein the control signal generation circuit is configured to generate a clock signal, and wherein the first end of the capacitor is connected to the drain of the first PMOS transistor and is connected to the drain of the second NMOS transistor as the output ends of the clock distribution sub-circuits.

### Claim 4 (depends on 1)

The multi-channel clock distribution circuit according to claim 1, wherein each of the first switch, the second switch, and the third switch is a transistor.

### Claim 5 (depends on 1)

The multi-channel clock distribution circuit according to claim 1, wherein each of the first switch, the second switch, and the third switch is a complementary metal oxide semiconductor (CMOS) transmission gate.

### Claim 6 (depends on 1)

The multi-channel clock distribution circuit according to claim 1, wherein the first switch is connected when the first clock signal is a first level signal and the first switch is disconnected when the first clock signal is a second level signal.

### Claim 7 (depends on 6)

The multi-channel clock distribution circuit according to claim 6, wherein each of the first switch and the third switch are not simultaneously in a connected state from a start moment to an end moment, wherein the start moment is when the second clock signal is the first level signal, and wherein the end moment is when the second clock signal is the first level signal.

### Claim 8 (depends on 7)

The multi-channel clock distribution circuit according to claim 7, wherein from the start moment to the end moment, a switchover of the first clock signal from a third level signal to a fourth level signal occurs at least once.

### Claim 9 (depends on 8)

The multi-channel clock distribution circuit according to claim 8, wherein from the start moment to the end moment, a switchover of the third clock signal from a sixth level signal to a fifth level signal occurs only once.

### Claim 10 (depends on 6)

The multi-channel clock distribution circuit according to claim 6, wherein the second switch is connected when the second clock signal is a third level signal and the second switch is disconnected when the second clock signal is a fourth level signal.

### Claim 11 (depends on 10)

The multi-channel clock distribution circuit according to claim 10, wherein the third switch is connected when the third clock signal is a fifth level signal and the third switch is disconnected when the third clock signal is a sixth level signal.