# US 10,122,349 B1 · Multi-mode power train integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,122,349 B1 - Document ID: US10122349B1 - Status: Granted - Kind: B1 - Application number: 15/677,989 - Filed: 2017-08-15 - Granted: 2018-11-06 - Earliest claimed: 2017-08-15 - Assignees: WiTricity Corporation - Applicants: WiTricity Corporation - Inventors: Lawrence Der; Sanjay Gupta - Web page: https://patentgrep.com/patent/US10122349B1 ## CPC - H03K 3/356182: {with additional means for controlling the main nodes} - G05F 3/205: {Substrate bias-voltage generators (for static stores G11C5/146)} - H03K 3/35613: {the input circuit having a differential configuration} - H03K 17/102: {in field-effect transistor switches} - H03K 19/00315: {in field-effect transistor circuits} - H03K 19/01721: {by means of a pull-up or down element} - H03K 19/09429: {one of the states being the high impedance or floating state} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract A configurable driver integrated circuit is disclosed having a plurality of input/output terminals for interfacing exterior of the integrated circuit. The integrated circuit includes a plurality of driver circuits, with each driver circuit including a transistor having a source and a drain, and each of the source and drain thereof connected to a dedicated and respective one of the input/output terminals and further includes a gate driver for driving a gate of the transistor, with supply inputs associated with a floating voltage domain, and each driver circuit also includes a level shift circuit for shifting the level of a logic signal from a fixed voltage domain to the floating voltage domain. A switching circuitry generates switching signals in a fixed voltage domain for controlling the operation of each of the driver circuits in accordance with a predetermined configuration defined by external circuit. ## Claims ### Claim 1 A configurable driver integrated circuit, comprising: a plurality of input/output terminals for interfacing exterior of the integrated circuit; a plurality of driver circuits, each driver circuit including: a transistor having a source and a drain, and each of the source and drain thereof connected to a dedicated and respective one of the input/output terminals, a gate driver for driving a gate of the transistor, and having supply inputs associated with a galvanically isolated floating voltage domain, and a level shift circuit for shifting the level of an input logic signal from a fixed voltage domain to the galvanically isolated floating voltage domain, which galvanically isolated floating voltage domain is galvanically isolated from the fixed voltage domain, the level shift circuit to drive an input of the gate driver in the galvanically isolated floating voltage domain; and logic circuitry for generating logic signals in the fixed voltage domain for driving the inputs of the level shift circuits and controlling the operation of each of the driver circuits in accordance with a predetermined configuration defined by external circuit components configuring the driver circuits in a predefined driver class to drive a load. ### Claim 2 (depends on 1) The driver integrated circuit of claim 1, wherein the load contains an inductive component. ### Claim 3 (depends on 1) The configurable integrated circuit of claim 1, wherein the transistor for each of the gate drivers comprises an NFET. ### Claim 4 (depends on 1) The configurable integrated circuit of claim 1, wherein the level shift circuit has a programmable delay associated there with. ### Claim 5 (depends on 4) The configurable integrated circuit of claim 4, wherein the level shift circuit is programmable to selectively disable the output thereof. ### Claim 6 (depends on 1) The configurable integrated circuit of claim 1, wherein one of the input/output terminals is connected to a positive and fixed external supply voltage and one of the input/output terminals is connected to a negative and fixed external supply voltage, both the positive and negative fixed external supply voltages existing in the fixed voltage domain. ### Claim 7 (depends on 1) The configurable integrated circuit of claim 1, wherein the gate driver has a negative supply voltage and a positive supply voltage, the negative supply voltage connected to the source of the associated transistor such that both the negative supply voltage of the gate driver and the source of the transistor are connected to the same one of the input/output terminals and wherein the positive supply voltage thereof is connected to a dedicated input/output terminal. ### Claim 8 (depends on 7) The configurable integrated circuit of claim 7, and further comprising a reference voltage generator operating in the fixed voltage domain for generating internal reference voltages to the integrated circuit and wherein, for at least one driver circuit, the associated gate driver circuit has associated there with a first coupling circuit for coupling the positive supply of the gate driver with an internally generated reference voltage when the positive supply of the gate driver is below or at the internally generated reference voltage and, when the supply of the gate driver is above the internally generated reference voltage, the positive supply of the gate driver is uncoupled from the internally generated reference voltage. ### Claim 9 (depends on 8) The configurable integrated circuit of claim 8, wherein, for the at least one driver circuit, the associated transistor has the drain thereof associated with a second coupling circuit for coupling the drain thereof with an internally generated reference voltage when the drain thereof is below or at the internally generated reference voltage and, when the drain thereof is above the internally generated reference voltage, the drain thereof is uncoupled from the internally generated reference voltage. ### Claim 10 (depends on 9) The configurable integrated circuit of claim 9, wherein the first and second coupling circuits are diodes. ### Claim 11 (depends on 1) The configurable integrated circuit of claim 1, wherein the driver circuits are configured into at least first and second driver sets, wherein each of the first and second driver sets is comprised of two driver circuits, with the inputs of the level shift circuits existing in the fixed voltage domain and further comprising a fixed voltage domain gate driver for driving the associated two driver circuits and their level shift circuits in the fixed voltage domain. ### Claim 12 (depends on 11) The configurable integrated circuit of claim 11, and further comprising an input circuit for receiving input drive signals from an external digital circuit for driving the fixed voltage domain gate drivers for each of the first and second driver sets in a complementary fashion. ### Claim 13 (depends on 11) The configurable integrated circuit of claim 11, and further comprising an internal oscillator for generating driving signals for driving the inputs of the fixed voltage domain gate drivers for each of the first and second driver sets in a complementary fashion. ### Claim 14 A configurable driver integrated circuit, comprising: circuitry operating in a fixed power supply domain; a plurality of input/output terminals for interfacing exterior of the integrated circuit and including power supply input terminals interfacing with the fixed power supply domain; a plurality of isolated driver circuits, each driver circuit including: a pair of transistors, each having a source and a drain, and each of the source and drain thereof connected to a dedicated and respective one of the input/output terminals, gate driver circuitry operating in a floating power supply domain relative to the fixed power supply domain for driving a gate of each of the transistors, and level shift circuitry for shifting the level of an input logic signal from the fixed voltage domain to the floating power supply domain for input to the gate driver in the associated floating voltage domain; and the circuitry operating in the fixed voltage power supply domain including logic circuitry for generating logic signals in the fixed voltage domain for driving the inputs of the level shift circuit in each of the driver circuits and controlling the operation of each of the driver circuits in accordance with a predetermined configuration defined by external circuit components configuring the driver circuits in a predefined driver class to drive a load. ### Claim 15 (depends on 14) The configurable driver integrated circuit of claim 14, wherein the gate driver circuitry in each of the driver circuits includes: a first gate driver for driving the gate of a first one of the pair of transistors; and a second gate driver circuit for driving a gate of a second one of the pair of transistors. ### Claim 16 (depends on 15) The configurable driver integrated circuit of claim 15, wherein the floating power supply domain for each of the driver circuits comprises first and second floating power supplies, one associated with each of the first and second gate drivers and wherein the level shift circuitry comprises a first level shift circuit for shifting the logic level of the input signal to a logic level compatible with the first floating power supply and a second level shift circuit for shifting the logic level of the input signal to a logic level compatible with the second floating power supply. ### Claim 17 (depends on 16) The configurable driver integrated circuit of claim 16, wherein the second gate driver can be disabled. ### Claim 18 (depends on 14) The configurable driver integrated circuit of claim 14, wherein there are two isolated driver circuits, first and second isolated driver circuits, the first isolated driver circuit associated with a first input signal and the second isolated driver circuit associated with a second input signal, wherein the first isolated driver circuit is associated with driving a first side of a load and the second isolated driver circuit is associated with driving a second side of the load circuit wherein the first and second input signals are out of phase with each other. ### Claim 19 (depends on 18) The configurable driver integrated circuit of claim 18, wherein the first input signal is a pulse signal and a second input signal is a pulse signal, wherein there is provided a first delay between a falling edge of the first input signal and a leading edge of the second input signal and a second delay between a falling edge of the second input signal and a leading edge of the first input signal.