# US 10,122,347 B2 · Adaptive voltage system for aging guard-band reduction

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- Number: US 10,122,347 B2
- Document ID: US10122347B2
- Status: Granted
- Kind: B2
- Application number: 15/477,913
- Filed: 2017-04-03
- Published: 2018-10-04
- Granted: 2018-11-06
- Earliest claimed: 2017-04-03
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Minki Cho; Jaydeep Kulkarni; Carlos Tokunaga; Muhammad Khellah; James Tschanz
- Web page: https://patentgrep.com/patent/US10122347B2

## CPC

- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C 11/419: Read-write [R-W] circuits
- G11C 29/06: Acceleration testing
- G11C 29/12005: {comprising voltage or current generators}
- G11C 29/24: Accessing extra cells, e.g. dummy cells or redundant cells
- G11C 29/46: Test trigger logic
- G11C 29/50012: {of timing}
- G11C 29/50016: {of retention}
- G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)}
- G11C 7/227: {Timing of memory operations based on dummy memory elements or replica circuits}
- G11C 2029/0401: {in embedded memories}
- G11C 2029/0409: {Online test}
- G11C 2029/5004: {Voltage}
- G11C 2029/5006: {Current}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An apparatus is provided which includes: a first power supply node; a second power supply node; a memory bit-cell coupled to the second power supply node; a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode; and a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell.

## Claims

### Claim 1

An apparatus comprising:
a first power supply node;
a second power supply node;
a memory bit-cell coupled to the second power supply node;
circuitry coupled to the first and second power supply nodes, wherein the circuitry is to operate in a diode-connected mode;
a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell; and
a sense amplifier to determine a logic state stored in the memory bit-cell before and after the application of the voltage and/or current stress to the memory bit-cell, wherein an output of the sense amplifier is to indicate an early detection of memory failure during a standby or retention mode.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising a power management circuitry to generate the digital signal such that the transistor is to turn on in a low power mode or retention mode, and to turn off in an active mode.

### Claim 3 (depends on 2)

The apparatus of claim 2, further comprising a voltage regulator coupled to the power management circuitry, wherein the voltage regulator is to provide a power supply to the first power supply node.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the power management circuitry is to instruct the voltage regulator to adjust the power supply according to an output of the sense amplifier associated with the memory bit-cell.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the power management circuitry is to adjust a value of a voltage identification (VID) code to adjust the power supply.

### Claim 6 (depends on 2)

The apparatus of claim 2, wherein the power management circuitry is to cause a power supply on the first power supply node to rise over time.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the memory bit-cell is a static random access memory bit-cell.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the circuitry comprises one of: a stack of diode-connected transistors, or a single diode-connected transistor.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the circuitry and the transistor are shared by a column of memory bit-cells.

### Claim 10

An apparatus comprising:
a first power supply node; and
a retention Vmin monitor (RVM) coupled to a memory, wherein the RVM is to detect an aging failure of the memory, wherein the RVM and the memory are coupled to the first power supply node, and wherein the RVM comprises:
a bit-cell coupled to a second power supply node;
circuitry coupled to the first and second power supply nodes, wherein the circuitry is to operate in a diode-connected mode; and
a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the bit-cell.

### Claim 11 (depends on 10)

The apparatus of claim 10, further comprising a tunable replica bit (TRB) circuitry coupled to the memory, wherein the TRB circuitry is to detect timing margin for the memory.

### Claim 12 (depends on 11)

The apparatus of claim 11, further comprising a tunable replica circuit (TRC) coupled to a logic block, wherein the TRC is to detect a timing margin and error in advance for the logic block, and wherein the logic block and the TRC are coupled to the first power supply node.

### Claim 13 (depends on 12)

The apparatus of claim 12, further comprising a power management circuitry communicatively coupled to the TRB circuitry, TRC, and RVM.

### Claim 14 (depends on 13)

The apparatus of claim 13, further comprising a voltage regulator coupled to the power management logic, wherein the power management circuitry is to cause the voltage regulator to modulate a power supply provided to the first power supply node according to outputs of the TRB, TRC, and RVM.

### Claim 15

A system comprising:
a voltage regulator;
a power management circuitry coupled to the voltage regulator;
a first power supply node coupled to the voltage regulator; and
a processor coupled to the first power supply node and the power management circuitry, wherein the processor includes a memory having a memory bit-cell coupled to the first and second power supply nodes, wherein the processor comprises:
a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode;
a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell; and
a sense amplifier to determine a logic state stored in the memory bit-cell before and after the application of the voltage and/or current stress to the memory bit-cell, wherein an output of the sense amplifier is to indicate an early detection of failure of the memory during a standby or retention mode.

### Claim 16 (depends on 15)

The system of claim 15, comprises a wireless interface to allow the processor to communicate with another device.

### Claim 17 (depends on 15)

The system of claim 15, wherein the power management circuitry is to generate the digital signal such that the transistor is to turn on in a low power mode or retention mode, and to turn off in an active mode.

### Claim 18 (depends on 15)

The system of claim 15, wherein the memory includes a column of memory bit cells, wherein the circuitry and the transistor are shared by the column of memory bit cells.