# US 10,122,345 B2 · Co-integrated bulk acoustic wave resonators > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,122,345 B2 - Document ID: US10122345B2 - Status: Granted - Kind: B2 - Application number: 14/392,126 - Filed: 2014-06-26 - Published: 2016-06-30 - Granted: 2018-11-06 - Earliest claimed: 2013-06-26 - Assignees: The Trustees of Columbia University in the City of New York - Applicants: The Trustees of Columbia University in the City of New York - Inventors: Hassan Edrees; Ioannis Kymissis; Peter Kinget - Web page: https://patentgrep.com/patent/US10122345B2 ## CPC - H03H 11/04: Frequency selective two-port networks - H03H 9/0547: {consisting of a vertical arrangement (H03H9/0566 takes precedence)} - H03H 9/17: having a single resonator (crystal tuning forks H03H9/21) - H03H 9/205: having multiple resonators (crystal tuning forks H03H9/21) - H03H 9/2426: {in combination with other electronic elements} - H03H 9/465: {in combination with other electronic elements} - H03H 9/467: {Post-fabrication trimming of parameters, e.g. center frequency} - H03H 9/525: {for microelectro-mechanical filters} - H03H 9/545: {including active elements} - H03H 9/605: {consisting of a ladder configuration} - H10N 30/706: {characterised by the underlying bases, e.g. substrates} - H10N 39/00: Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N30/00 – H10N35/00 - H03H 2009/02188: {Electrically tuning} - H03H 2009/02496: {Horizontal, i.e. parallel to the substrate plane} - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract An electrical circuit assembly can include a semiconductor integrated circuit, such as fabricated including CMOS devices. A first lateral-mode resonator can be fabricated upon a surface of the semiconductor integrated circuit, such as including a deposited acoustic energy storage layer including a semiconductor material, a deposited piezoelectric layer acoustically coupled to the deposited acoustic energy storage layer, and a first conductive region electrically coupled to the deposited piezoelectric layer and electrically coupled to the semiconductor integrated circuit. The semiconductor integrated circuit can include one or more transistor structures, such as fabricated prior to fabrication of the lateral-mode resonator. Fabrication of the lateral-mode resonator can include low-temperature processing specified to avoid disrupting operational characteristics of the transistor structures. ## Claims ### Claim 1 An electrical circuit assembly, comprising: a semiconductor integrated circuit; and a first lateral-mode resonator fabricated upon a surface of the semiconductor integrated circuit, the first lateral-mode resonator comprising: a deposited acoustic energy storage layer comprising a semiconductor layer; a deposited piezoelectric layer acoustically coupled to the deposited acoustic energy storage layer; a first conductive region electrically coupled to the deposited piezoelectric layer and electrically coupled to the semiconductor integrated circuit; and an acoustic mirror located between the deposited acoustic energy storage layer and the semiconductor integrated circuit; wherein the semiconductor integrated circuit includes one or more transistor structures. ### Claim 2 (depends on 1) The electrical circuit assembly of claim 1, wherein the semiconductor integrated circuit comprises complementary metal-oxide-semiconductor (CMOS) devices. ### Claim 3 (depends on 1) The electrical circuit assembly of claim 1, wherein the semiconductor layer of the deposited acoustic storage layer comprises a silicon layer. ### Claim 4 (depends on 1) The electrical circuit assembly of claim 1, comprising: a dielectric region located upon a surface of the semiconductor integrated circuit, the dielectric region coupled to the deposited acoustic energy storage layer and defining a cavity between the deposited acoustic energy storage layer and the semiconductor integrated circuit; wherein the acoustic energy storage layer includes a released configuration suspended from the dielectric region. ### Claim 5 (depends on 1) The electrical circuit assembly of claim 1, comprising a second lateral-mode resonator fabricated upon the semiconductor integrated circuit and electrically coupled to the semiconductor integrated circuit, the second lateral-mode resonator having one or more lateral dimensions that are different from the first lateral-mode resonator. ### Claim 6 (depends on 1) The electrical circuit assembly of claim 1, comprising the first lateral-mode resonator being included in an array of lateral-mode resonators fabricated upon the semiconductor integrated circuit; wherein at least some of the lateral-mode resonators are coupled to the semiconductor integrated circuit or to one another. ### Claim 7 (depends on 6) The electrical circuit assembly of claim 6, wherein the semiconductor integrated circuit includes a transistor-based switch circuit configured to establish a signal path including a selected one or more of the lateral-mode resonators included in the array. ### Claim 8 (depends on 6) The electrical circuit assembly of claim 6, wherein the semiconductor integrated circuit includes a transistor-based switch circuit configured to select amongst two or more filter circuits, the filter circuits including a specified one or more of the lateral-mode resonators included in the array. ### Claim 9 (depends on 1) The electrical circuit assembly of claim 1, comprising a second resonator having a structure and impedance different from the first lateral-mode resonator. ### Claim 10 (depends on 9) The electrical circuit assembly of claim 9, wherein the second resonator comprises a bulk acoustic wave resonator fabricated upon the semiconductor integrated circuit and electrically coupled to one or more of the first lateral-mode resonator or the semiconductor integrated circuit. ### Claim 11 (depends on 1) The electrical circuit assembly of claim 1, wherein the first lateral-mode resonator is electrically coupled to the semiconductor integrated circuit without requiring use of a wire bond; and wherein the first lateral-mode resonator and semiconductor integrated circuit share a common semiconductor substrate. ### Claim 12 (depends on 11) The electrical circuit assembly of claim 11, wherein the first lateral-mode resonator is electrically-coupled to the semiconductor integrated circuit using a via structure included as a portion of the first lateral-mode resonator coupled to a pad on the semiconductor integrated circuit. ### Claim 13 (depends on 1) The electrical circuit assembly of claim 1, wherein the deposited piezoelectric layer comprises ZnO; and wherein the semiconductor material of the deposited acoustic energy storage layer comprises one of a polycrystalline silicon layer or a silicon carbide layer. ### Claim 14 (depends on 1) The electrical circuit assembly of claim 1, wherein the semiconductor layer of the deposited acoustic energy storage layer comprises silicon carbide. ### Claim 15 An electrical circuit assembly, comprising: a semiconductor integrated circuit including complementary metal-oxide-semiconductor (CMOS) transistor structures; and an array of lateral-mode resonators fabricated upon the semiconductor integrated circuit, including a first lateral-mode resonator fabricated upon a surface of the semiconductor integrated circuit, the first lateral-mode resonator comprising: a deposited acoustic energy storage layer comprising a semiconductor layer; a deposited piezoelectric layer acoustically coupled to the deposited acoustic energy storage layer; a first conductive region electrically coupled to the deposited piezoelectric layer and electrically coupled to at least one of the transistor structures of the semiconductor integrated circuit; and an acoustic mirror located between the deposited acoustic energy storage layer and the semiconductor integrated circuit. ### Claim 16 (depends on 15) The electrical circuit assembly of claim 15, comprising: a dielectric region located upon a surface of the semiconductor integrated circuit, the dielectric region coupled to the deposited acoustic energy storage layer and defining a cavity between the deposited acoustic energy storage layer and the semiconductor integrated circuit; wherein the acoustic energy storage layer includes a released configuration suspended from the dielectric region. ### Claim 17 A method, comprising: forming an acoustic energy storage layer upon a surface of a semiconductor integrated circuit using a low-temperature deposition technique, the low-temperature deposition technique including a maximum temperature specified not to disrupt operating characteristics of transistor structures included as a portion of the semiconductor integrated circuit; forming a piezoelectric layer acoustically coupled to the deposited acoustic energy storage layer; forming a first conductive region electrically coupled to the deposited piezoelectric layer and electrically coupled to the semiconductor integrated circuit; wherein the acoustic energy storage layer, the piezoelectric layer, and the first conductive region are included as a portion of a first lateral-mode resonator; wherein forming the acoustic energy storage layer comprises recrystallizing a deposited semiconductor material using a laser. ### Claim 18 (depends on 17) The method of claim 17, comprising forming an array of lateral-mode resonators upon the surface of the semiconductor integrated circuit, the array including the first lateral mode resonator; and wherein the semiconductor integrated circuit includes complementary metal-oxide-semiconductor (CMOS) transistor structures. ### Claim 19 (depends on 17) The method of claim 17, comprising: forming a dielectric region located upon a surface of the semiconductor integrated circuit, the dielectric region coupled to the deposited acoustic energy storage layer and defining a cavity between the deposited acoustic energy storage layer and the semiconductor integrated circuit; wherein the acoustic energy storage layer includes a released configuration suspended from the dielectric region. ### Claim 20 (depends on 17) The method of claim 17, comprising: forming an acoustic mirror located between the deposited acoustic energy storage layer and the semiconductor integrated circuit. ### Claim 21 (depends on 17) The method of claim 17, wherein a temperature used for forming the acoustic energy storage layer is less than about 450 degrees Celsius. ### Claim 22 (depends on 17) The method of claim 17, wherein a temperature used for forming the acoustic energy storage layer is less than about 400 degrees Celsius. ### Claim 23 (depends on 17) The method of claim 17, wherein the temperature used for forming the acoustic energy storage layer is no greater than 70 degrees Celsius.