# US 10,122,318 B2 · System on-chip for controlling motor based on network and method for controlling thereof

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- Number: US 10,122,318 B2
- Document ID: US10122318B2
- Status: Granted
- Kind: B2
- Application number: 14/760,502
- Filed: 2013-04-24
- Published: 2015-12-10
- Granted: 2018-11-06
- Earliest claimed: 2013-02-12
- Assignees: Ajinextek Co., Ltd.
- Applicants: Ajinextek Co., Ltd
- Inventors: Kwang Ju Sung; Chang Ho Kim; Sung Hyuk Choi; Sang Tae Lee
- Web page: https://patentgrep.com/patent/US10122318B2

## CPC

- H02P 31/00: Arrangements for regulating or controlling electric motors not provided for in groups H02P1/00 - H02P5/00, H02P7/00 or H02P21/00 - H02P29/00
- G05B 15/02: electric
- H04L 67/125: involving control of end-device applications over a network
- H02P: CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A network-based motor control system-on-chip (SoC) and a motor control method. The network-based motor control system includes a network unit; a first processor for exchanging a first data with the network unit and processing a first task related to the first data; a motor; a motor control unit for controlling operation of the motor; a second processor for exchanging a second data related to the operation of the motor with the motor control unit and processing a second task related to the second data; and a data sharing unit for sharing processing results of the first task and the second task by the first processor and the second processor, in which the first task and the second task are concurrently processed.

## Claims

### Claim 1

A network-based motor control system-on-chip (SOC) system comprising:
a first processor configured to exchange a first data with a network unit and configured to process a first task related to the first data;
a motor control unit configured to control operation of a motor;
a second processor configured to
exchange a second data related to the operation of the motor with the motor control unit and configured to process a second task related to the second data and
create an initial reference position of the motor, and the motor control unit is configured to control operation of the motor by comparing a current position of the motor with the initial reference position provided by the second processor; and
a shared memory unit configured to share processing results of the first task and the second task by the first processor and the second processor,
wherein the first task and the second task are configured to be concurrently processed, and
wherein the motor control unit is configured to one of
inform the second processor that the motor has moved to a correct position by generating an interrupt signal if the current position of the motor is equal to the reference position, or
control to change a position of the motor if the current position of the motor is different from the reference position.

### Claim 2 (depends on 1)

The system according to claim 1, wherein the motor control unit includes a plurality of pieces of hardware respectively corresponding to a plurality of operation functions based on firmware configured as logic to process the second data, and the plurality of pieces of hardware is configured as a System-On-Chip (SoC).

### Claim 3 (depends on 2)

The system according to claim 2, wherein the plurality of operation functions includes
an analog to digital (ADC) conversion function,
a digital to analog (DAC) conversion function,
a general-purpose input/output (GPIO) function,
a Capture & Compare function,
a Space Vector Pulse Width Modulation (SVPWM) function,
an Encoder Interpolation function,
a Profile Generation function, and
a Digital Quotient (DQ) conversion function.

### Claim 4 (depends on 1)

The system according to claim 1, wherein the shared memory unit is configured to allow the processing results of the first task and the second task to be shared.

### Claim 5 (depends on 4)

The system according to claim 4, wherein the sharing the processing results of the first task and the second task is configured to be an edge interrupt method between the first processor and the second processor.

### Claim 6

A network-based motor control method comprising the steps of:
exchanging a first data with a network unit by a first processor and exchanging a second data related to operation of a motor with a motor control unit by a second processor;
processing a first task related to the first data by the first processor;
processing a second task related to the second data by the second processor;
creating an initial reference position of the motor by the second processor;
one of
informing the second processor that the motor has moved to a correct position by generating an interrupt signal if a current position of the motor is equal to the reference position, or
controlling to change a position of the motor if the current position of the motor is different from the reference position, by the motor control unit; and
sharing processing results of the first task by the first processor and processing results of the second task by the second processor through a shared memory unit,
wherein the first task and the second task are concurrently processed.

### Claim 7 (depends on 6)

The method according to claim 6, wherein the shared memory unit allows the processing results of the first task and the second task to be shared, and a method of sharing the processing results of the first task and the second task is an edge interrupt method between the first processor and the second processor.