# US 10,122,294 B2 · Active gate clamping for inverter switching devices with enhanced common source inductance > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,122,294 B2 - Document ID: US10122294B2 - Status: Granted - Kind: B2 - Application number: 15/366,266 - Filed: 2016-12-01 - Published: 2018-06-07 - Granted: 2018-11-06 - Earliest claimed: 2016-12-01 - Assignees: Ford Global Technologies, LLC - Applicants: Ford Global Technologies, LLC - Inventors: Zhuxian Xu; Chingchi Chen; Michael W. Degner - Web page: https://patentgrep.com/patent/US10122294B2 ## CPC - H02M 7/537: using semiconductor devices only, e.g. single switched pulse inverters - H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters - H02M 1/32: Means for protecting converters other than automatic disconnection - H02M 1/38: Means for preventing simultaneous conduction of switches - H02M 7/003: {Constructional details, e.g. physical layout, assembly, wiring or busbar connections} - H02M 7/5387: in a bridge configuration - H02M 1/342: {Active non-dissipative snubbers} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires} - Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS ## Abstract An inverter phase leg has upper and lower gate drive circuits supplying gate drive signals to upper and lower transistors. Each gate drive circuit includes an active clamp for selectively deactivating the upper and lower transistors. The transistors are comprised of semiconductor devices, each having respective gate, source, and emitter terminals. Each emitter terminal is connected to a respective output electrode structured to enhance a common source inductance between the respective gate and emitter terminals. Each emitter terminal is further connected to a respective Kelvin emitter electrode substantially bypassing the respective output electrode. Each respective active clamp is connected between the respective gate terminal and Kelvin emitter electrode so that the active clamping function remains effective in the presence of the enhanced common source inductance. ## Claims ### Claim 1 An inverter comprising; a phase leg having series-connected upper and lower transistors adapted to be connected between positive and negative DC buses; and upper and lower gate drive circuits supplying gate drive signals to the upper and lower transistors, respectively, and each including an active clamp for deactivating the upper and lower transistors, respectively; wherein the transistors are comprised of semiconductor devices, each having respective gate, source, and emitter terminals; wherein each emitter terminal is connected to a respective output electrode structured to enhance a common source inductance between the respective gate and emitter terminals; wherein each emitter terminal is further connected to a respective Kelvin emitter electrode substantially bypassing the respective output electrode; and wherein each respective active clamp is connected between the respective gate terminal and Kelvin emitter electrode. ### Claim 2 (depends on 1) The inverter of claim 1 further comprising upper and lower gate resistors coupling the gate drive signals between the upper and lower gate drive circuits and the upper and lower transistors, respectively, wherein the active clamp is connected to a junction between the gate terminal and the gate resistor. ### Claim 3 (depends on 1) The inverter of claim 1 further comprising upper and lower gate resistors coupling the gate drive signals between the upper and lower gate drive circuits and the upper and lower transistors, respectively, wherein the gate resistors are connected between the respective output electrode and gate drive circuit, wherein each gate terminal is connected to a respective gate electrode, wherein each gate electrode is directly connected to the respective gate drive circuit to receive the respective gate drive signal and to connect with the respective active clamp. ### Claim 4 (depends on 1) The inverter of claim 1 wherein each Kelvin emitter electrode is comprised of a respective Kelvin emitter pin connected by a respective first bonded wire to a pad for the respective emitter terminal on the respective semiconductor device, and wherein each output electrode is comprised of an emitter control pin connected by a respective second bonded wire to a respective power strip. ### Claim 5 (depends on 4) The inverter of claim 4 wherein the first bonded wires have a length shorter than the second bonded wires. ### Claim 6 (depends on 1) The inverter of claim 1 wherein each respective active clamp is comprised of a MOSFET and an RC filter connected to a gate of the MOSFET. ### Claim 7 (depends on 6) The inverter of claim 6 wherein each respective active clamp further comprises a recovery diode connected across a resistor of the RC filter. ### Claim 8 A power converter comprising: a DC link with positive and negative buses configured to receive a DC supply voltage; a plurality of phase legs in a bridge configuration coupled between the positive and negative buses, each phase leg having series-connected upper and lower transistors with an intermediate junction providing a phase leg output; and upper and lower gate drive circuits for each phase leg supplying gate drive signals to the upper and lower transistors, respectively, wherein each drive circuit includes an active clamp for deactivating the upper and lower transistors, respectively; wherein the transistors are comprised of semiconductor devices and each having respective gate, source, and emitter terminals; wherein each emitter terminal is connected to a respective output electrode structured to enhance a common source inductance between the respective gate and emitter terminals; wherein each emitter terminal is further connected to a respective Kelvin emitter electrode substantially bypassing the output electrode structure; and wherein each respective active clamp is connected between the respective gate terminal and Kelvin emitter electrode. ### Claim 9 (depends on 8) The power converter of claim 8 wherein each phase leg further comprises upper and lower gate resistors coupling respective gate drive signals between the upper and lower gate drive circuits and the upper and lower transistors, respectively, wherein each respective active clamp is connected to a respective junction between the respective gate terminal and the gate resistor. ### Claim 10 (depends on 8) The power converter of claim 8 wherein each phase leg further comprises upper and lower gate resistors coupling the gate drive signals between the upper and lower gate drive circuits and the upper and lower transistors, respectively, wherein the gate resistors are connected between the respective output electrode and gate drive circuit, wherein each gate terminal is connected to a respective gate electrode, wherein each gate electrode is directly connected to the respective gate drive circuit to receive the respective gate drive signal and to connect with the respective active clamp. ### Claim 11 (depends on 8) The power converter of claim 8 wherein each Kelvin emitter electrode is comprised of a respective Kelvin emitter pin connected by a respective first bonded wire to a pad for the respective emitter terminal on the respective semiconductor device, and wherein each output electrode is comprised of an emitter control pin connected by a respective second bonded wire to a respective power strip. ### Claim 12 (depends on 11) The power converter of claim 11 wherein the first bonded wires have a length shorter than the second bonded wires. ### Claim 13 (depends on 8) The power converter of claim 8 wherein the transistors are each comprised of an insulated gate bipolar transistor (IGBT). ### Claim 14 (depends on 8) The power converter of claim 8 wherein each respective active clamp is comprised of a MOSFET and an RC filter connected to a gate of the MOSFET. ### Claim 15 (depends on 14) The power converter of claim 14 wherein each respective active clamp further comprises a recovery diode connected across a resistor of the RC filter. ### Claim 16 An inverter comprising; a bridge having upper and lower transistors; and upper and lower gate drive circuits including active clamps for deactivating the transistors; wherein each transistor has an output electrode structured to enhance a common source inductance of the transistor; wherein each transistor has a Kelvin emitter electrode substantially bypassing the respective output electrode; and wherein each active clamp is connected between a gate terminal and Kelvin emitter electrode of the respective transistor. ### Claim 17 (depends on 16) The inverter of claim 16 further comprising upper and lower gate resistors coupling the gate drive signals between the upper and lower gate drive circuits and the upper and lower transistors, respectively, wherein the active clamp is connected to a junction between the gate terminal and the gate resistor. ### Claim 18 (depends on 16) The inverter of claim 16 further comprising upper and lower gate resistors coupling the gate drive signals between the upper and lower gate drive circuits and the upper and lower transistors, respectively, wherein the gate resistors are connected between the respective output electrode and gate drive circuit, wherein each gate terminal is connected to a respective gate electrode, wherein each gate electrode is directly connected to the respective gate drive circuit to receive the respective gate drive signal and to connect with the respective active clamp. ### Claim 19 (depends on 16) The inverter of claim 16 wherein each respective active clamp is comprised of a MOSFET and an RC filter connected to a gate of the MOSFET. ### Claim 20 (depends on 19) The inverter of claim 19 wherein each respective active clamp further comprises a recovery diode connected across a resistor of the RC filter.