# US 10,122,279 B2 · Inverting buck-boost converter drive circuit and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,122,279 B2 - Document ID: US10122279B2 - Status: Granted - Kind: B2 - Application number: 15/592,757 - Filed: 2017-05-11 - Published: 2017-08-31 - Granted: 2018-11-06 - Earliest claimed: 2014-10-24 - Assignees: STMicroelectronics (Shenzhen) R&D Co. Ltd - Applicants: STMicroelectronics (Shenzhen) R&D Co. Ltd - Inventors: Hai Bo Zhang; Jerry Huang - Web page: https://patentgrep.com/patent/US10122279B2 ## CPC - H02M 3/1582: {Buck-boost converters (H02M3/1584 takes precedence)} - H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters - H02M 3/158: including plural semiconductor devices as final control devices for a single load - H02M 1/0009: {Devices or circuits for detecting current in a converter} - H02M 1/0032: {Control circuits allowing low power mode operation, e.g. in standby mode} - H02M 3/156: with automatic control of output voltage or current, e.g. switching regulators - H03K 2217/0063: High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load - H03K 2217/0072: Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load - H03K 2217/0081: Power supply means, e.g. to the switch driver - Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS ## Abstract A driver circuit includes a high-side power transistor having a source-drain path coupled between a first node and a second node and a low-side power transistor having a source-drain path coupled between the second node and a third node. A high-side drive circuit, having an input configured to receive a drive signal, includes an output configured to drive a control terminal of said high-side power transistor. The high-side drive circuit is configured to operate as a capacitive driver. A low-side drive circuit, having an input configured to receive a complement drive signal, includes an output configured to drive a control terminal of said low-side power transistor. The low-side drive circuit is configured to operate as a level-shifting driver. ## Claims ### Claim 1 A circuit, comprising: a power transistor having a drain terminal coupled to a input node and a source terminal coupled to an output node; a drive circuit having an input configured to receive a drive signal and an output configured to output a first control signal; a first capacitor having a first terminal coupled to receive the first control signal from the drive circuit and a second terminal configured to generate a first boosted control signal at a first intermediate node; a diode having an anode coupled to the input node and a cathode coupled to the first intermediate node; a circuit path configured to apply the first boosted control signal from the first intermediate node to a gate terminal of the power transistor; an inverter circuit configured to invert the first control signal and generate a second control signal; a second capacitor having a first terminal coupled to receive the second control signal from the inverter circuit and a second terminal configured to generate a second boosted control signal at a second intermediate node; and a first transistor having a gate terminal coupled to receive the second boosted control signal from the second intermediate node, a drain terminal directly connected to the gate of the power transistor and a source terminal directly connected to the source terminal of the power transistor. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the drive circuit comprises a further inverter circuit having a second transistor coupled between the input node and the output of the drive circuit and a third transistor coupled between the output of the drive circuit and a ground reference node. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the second and third transistors form a logic inverter circuit. ### Claim 4 (depends on 1) The circuit of claim 1, wherein the circuit path coupling the first intermediate node to the gate terminal of the power transistor comprises a switch circuit operable to selectively connect the intermediate node to the gate terminal of the power transistor. ### Claim 5 (depends on 4) The circuit of claim 4, wherein the switch circuit comprises a fourth transistor having a source terminal coupled to the first intermediate node and a drain terminal coupled to the gate of the power transistor. ### Claim 6 (depends on 5) The circuit of claim 5, wherein a gate terminal of the fourth transistor is coupled to the input node. ### Claim 7 (depends on 1) The circuit of claim 1, further comprising a clamp diode coupled between the gate terminal of said first transistor and the source terminal of the power transistor. ### Claim 8 (depends on 7) The circuit of claim 7, further comprising a resistor coupled in parallel with the clamp diode. ### Claim 9 (depends on 1) The circuit of claim 1, further comprising a resistor coupled between the gate terminal and source terminal of the power transistor. ### Claim 10 (depends on 1) The circuit of claim 1, wherein said input node is configured to receive a power supply voltage. ### Claim 11 (depends on 1) The circuit of claim 1, wherein said output node is coupled to a load. ### Claim 12 (depends on 11) The circuit of claim 11, wherein the load is inductive. ### Claim 13 A circuit, comprising: a power transistor having a drain terminal coupled to an input node and a source terminal coupled to an output node; a drive circuit having an input configured to receive a drive signal and an output configured to output a first control signal; an inverter circuit configured to invert the first control signal and generate a second control signal; a first capacitor having a first terminal coupled to receive the first control signal from the drive circuit and a second terminal configured to generate a first boosted control signal for application to a gate of said power transistor; a first transistor having a drain terminal directly connected to the gate of the power transistor and a source terminal directly connected to the source terminal of the power transistor, said first transistor having a gate terminal; and a second capacitor having a first terminal coupled to receive the second control signal and a second terminal configured to generate a second boosted control signal for application to the gate terminal of the first transistor. ### Claim 14 (depends on 13) The circuit of claim 13, further comprising: a diode having an anode coupled to the input node and a cathode coupled to the second terminal of the first capacitor; and a switch circuit operable to selectively connect the second terminal of the first capacitor to the gate terminal of the power transistor. ### Claim 15 (depends on 14) The circuit of claim 14, wherein the switch circuit comprises a second transistor having a source terminal coupled to the second terminal of the first capacitor and a drain terminal coupled to the gate of the power transistor. ### Claim 16 (depends on 15) The circuit of claim 15, wherein a gate terminal of the second transistor is coupled to the input node. ### Claim 17 (depends on 15) The circuit of claim 15, wherein a voltage at the input node is applied to a gate terminal of the second transistor. ### Claim 18 (depends on 13) The circuit of claim 13, wherein the drive circuit comprises an inverter circuit. ### Claim 19 (depends on 13) The circuit of claim 13, further comprising a clamp diode coupled between the gate terminal of said first transistor and the source terminal of the power transistor. ### Claim 20 (depends on 19) The circuit of claim 19, further comprising a resistor coupled in parallel with the clamp diode. ### Claim 21 (depends on 13) The circuit of claim 13, further comprising a resistor coupled between the gate terminal and source terminal of the power transistor. ### Claim 22 A circuit, comprising: a power transistor having a drain terminal connected to an input node, a source terminal connected to an output node, and a gate terminal; a drive circuit configured to generate a first control signal and a second control signal that is a logical inversion of the first control signal; a first boot capacitor configured to receive the first control signal and generate a first boosted control signal that is applied to the gate terminal of said power transistor; a first transistor having a drain terminal connected to the gate of the power transistor, a source terminal connected to the source terminal of the power transistor, and a gate terminal; and a second boot capacitor configured to receive the second control signal and generate a second boosted control signal that is applied to the gate terminal of said first transistor. ### Claim 23 (depends on 22) The circuit of claim 22, further comprising a switching circuit connected in series with the first boot capacitor and configured to selectively apply the first boosted control signal to the gate terminal of said power transistor. ### Claim 24 (depends on 23) The circuit of claim 23, further comprising: a diode having an anode connected to the input node and a cathode connected to an intermediate node where the first boot capacitor is connected in series with the switching circuit. ### Claim 25 (depends on 22) The circuit of claim 22, wherein the switching circuit comprises a second transistor having a source terminal connected to the intermediate node and a drain terminal connected to the gate of the power transistor. ### Claim 26 (depends on 22) The circuit of claim 22, further comprising a clamp diode connected between the gate terminal of said first transistor and the source terminal of the power transistor. ### Claim 27 (depends on 26) The circuit of claim 26, further comprising a resistor connected in parallel with the clamp diode. ### Claim 28 (depends on 22) The circuit of claim 22, further comprising a resistor connected between the gate terminal of the power transistor and source terminal of the power transistor.