# US 10,122,272 B1 · Cycle skipping prevent circuit in a regulator of a DC-to-DC converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,122,272 B1 - Document ID: US10122272B1 - Status: Granted - Kind: B1 - Application number: 15/859,401 - Filed: 2017-12-30 - Granted: 2018-11-06 - Earliest claimed: 2017-12-30 - Assignees: Active-Semi, Inc. - Applicants: Active-Semi, Inc. - Inventors: Masashi Nogawa - Web page: https://patentgrep.com/patent/US10122272B1 ## CPC - H02M 3/157: with digital control - H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters - H02M 1/44: Circuits or arrangements for compensating for electromagnetic interference in converters or inverters - H02M 3/156: with automatic control of output voltage or current, e.g. switching regulators - H02M 3/158: including plural semiconductor devices as final control devices for a single load - H02M 1/0009: {Devices or circuits for detecting current in a converter} - H02M 3/1566: {with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation} - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract A DC-to-DC converter employs peak current mode control and includes a cycle skipping prevent circuit. If a latch is set, then a high side switch is turned on. A comparator receives a signal indicative of current flow and a compensated error signal. The prevent circuit supplies a delayed version of a low duty cycle, fixed frequency, oscillator signal onto the set input lead of the latch. The prevent circuit gates a high signal as output by the comparator onto the reset input lead of the latch. If the output of the comparator has, however, not transitioned high by a predetermined time, then the prevent circuit gates a high pulse onto the reset input lead. Accordingly, the prevent circuit ensures that the latch is reset once every period of the signal SET. A cycle skipping prevent circuit is also disclosed for use in a converter that employs valley current mode control. ## Claims ### Claim 1 A voltage regulator control circuit for controlling a DC-to-DC switching converter using a peak current (PC) mode, wherein the voltage regulator control circuit comprises: a sequential logic element having a set input lead, a reset input lead, and an output lead; a current sense circuit that outputs a voltage signal VCURRENT indicative of a magnitude of a current; a comparator circuit that has a first input lead, a second input lead, and an output lead, wherein the first input lead receives the voltage signal VCURRENT from the current sense circuit, wherein the comparator circuit outputs a RESET0 signal onto the comparator output lead; a signal conductor, wherein an oscillator signal OSC is present on the signal conductor; and a cycle skipping prevent circuit that receives the RESET0 signal and that receives the oscillator signal OSC, wherein the cycle skipping prevent circuit supplies a delayed version of the oscillator signal OSC onto the set input lead of the sequential logic element in a form of a signal SET, wherein the signal SET has a period that extends from a rising leading edge of a high pulse of the signal SET to a rising leading edge of a subsequent high pulse of the signal SET, wherein the cycle skipping prevent circuit gates a digital logic high signal as output by the comparator circuit onto the reset input lead of the sequential logic element if the RESET0 signal as output by the comparator circuit is at a digital logic high level, wherein in the period if the RESET0 signal has not transitioned to the digital logic high level by a predetermined time in the period then the cycle skipping prevent circuit gates the high pulse onto the reset input lead of the sequential logic element. ### Claim 2 (depends on 1) The voltage regulator control circuit of claim 1, wherein the cycle skipping prevent circuit gates the high pulse onto the reset input lead of the sequential logic element such that the digital logic high level on the reset input lead then returns to a digital logic low level before an end of the period. ### Claim 3 (depends on 1) The voltage regulator control circuit of claim 1, wherein the predetermined time is a time of an edge of the oscillator signal OSC. ### Claim 4 (depends on 1) The voltage regulator control circuit of claim 1, wherein the cycle skipping prevent circuit comprises: a digital logic gate that has an input lead and an output lead, wherein the digital logic gate receives the RESET0 signal onto its input lead, wherein the output lead of the digital logic gate is coupled to the reset input lead of the sequential logic element. ### Claim 5 (depends on 1) The voltage regulator control circuit of claim 1, wherein the cycle skipping prevent circuit comprises: a delay element that receives the oscillator signal OSC and that supplies the signal SET onto the set input lead of the sequential logic element; and a flip-flop having a clock input lead and a data input lead, wherein the data input lead of the flip-flop is coupled to the output lead of the sequential logic element, wherein the oscillator signal OSC is supplied onto the clock input lead of the flip-flop. ### Claim 6 (depends on 1) The voltage regulator control circuit of claim 1, wherein the cycle skipping prevent circuit receives a cycle skipping prevent enable signal, wherein the cycle skipping prevent enable signal is a single-bit digital signal, wherein if the cycle skipping prevent enable signal has a first digital logic level then the cycle skipping prevent circuit is enabled to gate the high pulse onto the set input lead of the sequential logic element if the RESET0 signal has not transitioned to the digital logic high level by the predetermined time in the period, wherein if the cycle skipping prevent enable signal has a second digital logic level then the cycle skipping prevent circuit is disabled from gating the high pulse onto the set input lead of the sequential logic element if the RESET0 signal has not transitioned to the digital logic high level by the predetermined time in the period. ### Claim 7 (depends on 1) The voltage regulator control circuit of claim 1, wherein the oscillator signal OSC is at the digital logic high level for less than twenty percent of the period, and is at a digital logic low level for more than eighty percent of the period. ### Claim 8 (depends on 1) The voltage regulator control circuit of claim 1, wherein the sequential logic element is a latch. ### Claim 9 (depends on 1) The voltage regulator control circuit of claim 1, wherein the comparator circuit receives a compensated error signal VE-C onto its second input lead. ### Claim 10 (depends on 1) The voltage regulator control circuit of claim 1, wherein the DC-to-DC switching converter includes a high side switch, wherein a digital signal output by the sequential logic element onto the output lead of the sequential logic element controls the high side switch. ### Claim 11 A voltage regulator control circuit for controlling a DC-to-DC switching converter, wherein the voltage regulator control circuit comprises: a sequential logic element having a set input lead, a reset input lead, and an output lead; a comparator circuit that has a first input lead, a second input lead, and an output lead, wherein the first input lead receives a voltage signal VCURRENT, wherein the voltage signal VCURRENT is indicative of a current flow in the DC-to-DC switching converter; a flip-flop having an oscillator signal input lead, a data input lead, and a data output lead; first logic gate circuitry having a first input lead, a second input lead, and an output lead, wherein the second input lead of the first logic gate circuitry is coupled to the data output lead of the flip-flop; second logic gate circuitry having a first input lead, a second input lead, and an output lead, wherein the second input lead of the second logic gate circuitry is coupled to receive a first signal from the output lead of the first logic gate circuitry, wherein the first input lead of the second logic gate circuitry is coupled to receive a second signal from the output lead of the comparator circuit, wherein the output lead of the second logic gate circuitry is coupled to supply a third signal onto the reset input lead of the sequential logic element; a delay element having an input lead and an output lead, wherein the output lead of the delay element is coupled to supply a fourth signal onto the set input lead of the sequential logic element; and a signal conductor that is coupled to the oscillator signal input lead of the flip-flop and to the first input lead of the first logic gate circuitry and to the input lead of the delay element. ### Claim 12 (depends on 11) The voltage regulator control circuit of claim 11, wherein the DC-to-DC switching converter includes a high side switch, wherein a digital signal output by the sequential logic element onto the output lead of the sequential logic element controls the high side switch. ### Claim 13 (depends on 11) The voltage regulator control circuit of claim 11, wherein an error compensated signal VE-C is present on the second input lead of the comparator circuit. ### Claim 14 (depends on 11) The voltage regulator control circuit of claim 11, wherein an oscillator signal OSC is present on the signal conductor, wherein the oscillator signal OSC has a period, wherein the oscillator signal OSC is at a first digital logic level for less than twenty percent of the period, and is at a second digital logic level for more than eighty percent of the period. ### Claim 15 (depends on 11) The voltage regulator control circuit of claim 11, wherein the first logic gate circuitry includes a first logic gate, and wherein the second logic gate circuitry includes a second logic gate. ### Claim 16 (depends on 11) The voltage regulator control circuit of claim 11, further comprising: a cycle skipping prevent circuit disable signal conductor, wherein if a second digital logic level is present on the cycle skipping prevent circuit disable signal conductor then the first signal on the output lead of the first logic gate circuitry is fixed and unchangeable, whereas if a first digital logic level is present on the cycle skipping prevent circuit disable signal conductor then the first signal present on the output lead of the first logic gate circuitry is changeable. ### Claim 17 A voltage regulator control circuit for controlling a DC-to-DC switching converter, wherein the voltage regulator control circuit comprises: a sequential logic element having a set input lead, a reset input lead, and an output lead; a comparator circuit that has a first input lead, a second input lead, and an output lead, wherein the first input lead receives a voltage signal VCURRENT, wherein the voltage signal VCURRENT is indicative of a magnitude of a current flowing in the DC-to-DC switching converter, wherein the comparator circuit outputs a RESET0 signal onto the comparator output lead; a signal conductor, wherein an oscillator signal OSC is present on the signal conductor; and means for receiving the RESET0 signal and for receiving the oscillator signal OSC, wherein the means is also for supplying a delayed version of the oscillator signal OSC onto the set input lead of the sequential logic element in a form of a signal SET, wherein the signal SET has a period that extends from a rising leading edge of a high pulse of the signal SET to a rising leading edge of a subsequent high pulse of the signal SET, wherein the means is also for gating a digital logic high signal as output by the comparator circuit onto the set input lead of the sequential logic element if the RESET0 signal as output by the comparator circuit is at a digital logic high level, wherein in the period if the RESET0 signal has not transitioned to the digital logic high level by a predetermined time in the period then the means gates the high pulse onto the set input lead of the sequential logic element. ### Claim 18 A voltage regulator control circuit for controlling a DC-to-DC switching converter using a peak current (PC) mode, wherein the voltage regulator control circuit is an integrated circuit, wherein the DC-to-DC switching converter comprises an inductor, wherein a switching current ISW flows through the inductor, and wherein the voltage regulator control circuit comprises: a sequential logic element having a set input lead, a reset input lead, and an output lead; a first signal conductor that carries a voltage signal VCURRENT, wherein the voltage signal VCURRENT is indicative of a magnitude of the switching current ISW; a comparator circuit that has a first input lead, a second input lead, and an output lead, wherein the first input lead receives the voltage signal VCURRENT and that outputs a RESET0 signal onto the comparator output lead; a second signal conductor that carries an oscillator signal OSC; and a cycle skipping prevent circuit that receives the RESET0 signal and that receives the oscillator signal OSC, wherein the cycle skipping prevent circuit supplies a delayed version of the oscillator signal OSC onto the set input lead of the sequential logic element in a form of a signal SET, wherein the signal SET has a period that extends from a rising leading edge of a high pulse of the signal SET to a rising leading edge of a subsequent high pulse of the signal SET, wherein the cycle skipping prevent circuit gates a digital logic high signal as output by the comparator circuit onto the reset input lead of the sequential logic element if the RESET0 signal as output by the comparator circuit is at a digital logic high level, wherein in the period if the RESET0 signal has not transitioned to the digital logic high level by a predetermined time in the period then the cycle skipping prevent circuit gates the high pulse onto the reset input lead of the sequential logic element. ### Claim 19 (depends on 18) The voltage regulator control circuit of claim 18, further comprising: a switching integrated circuit terminal SW; and a high side switch HSS that is coupled to the switching integrated circuit terminal SW, wherein the high side switch HSS receives a control signal from the sequential logic element, wherein the switching integrated circuit terminal SW and the high side switch HSS are both disposed on the integrated circuit. ### Claim 20 (depends on 18) The voltage regulator control circuit of claim 18, further comprising: a current sense circuit that outputs the voltage signal VCURRENT, wherein at least a part of the current sense circuit is disposed on the integrated circuit. ### Claim 21 (depends on 18) The voltage regulator control circuit of claim 18, further comprising: a third conductor that carries a cycle skipping prevent enable signal, wherein the cycle skipping prevent enable signal is a single-bit digital signal, wherein if the cycle skipping prevent enable signal has a first digital logic level then the cycle skipping prevent circuit is enabled whereas if the cycle skipping prevent enable signal has a second digital logic level then the cycle skipping prevent circuit is disabled, wherein the third conductor is disposed on the integrated circuit. ### Claim 22 (depends on 18) The voltage regulator control circuit of claim 18, further comprising: a cycle skipping prevent enable integrated circuit terminal CSPEN, wherein the cycle skipping prevent enable integrated circuit terminal CSPEN receives a cycle skipping prevent enable signal onto the integrated circuit, wherein the cycle skipping prevent enable signal is a single-bit digital signal, wherein if the cycle skipping prevent enable signal has a first digital logic level then the cycle skipping prevent circuit is enabled whereas if the cycle skipping prevent enable signal has a second digital logic level then the cycle skipping prevent circuit is disabled.