# US 10,122,266 B1 · Power supply charge pump and protection circuit

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- Number: US 10,122,266 B1
- Document ID: US10122266B1
- Status: Granted
- Kind: B1
- Application number: 14/929,181
- Filed: 2015-10-30
- Granted: 2018-11-06
- Earliest claimed: 2012-09-28
- Assignees: Maxim Integrated Products, Inc.
- Applicants: Maxim Integrated Products, Inc.
- Inventors: Marco Farina; Mauro Ranzato; Gianluca Mariano
- Web page: https://patentgrep.com/patent/US10122266B1

## CPC

- H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps}
- H02H 3/202: {for DC systems}
- H02H 7/20: for electronic equipment (for converters H02H7/10; for electric measuring instruments G01R1/36; for DC voltage or current semiconductor regulators G05F1/569; for amplifiers H03F1/52; for electronic switching circuits H03K17/08)
- H02H 11/003: {using a field effect transistor as protecting element in one of the supply lines}
- H02J 7/68: using circuits for correcting or protecting against reverse-polarity
- H02H 11/002: {in case of inverted polarity or connection; with switching for obtaining correct connection}
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H02J: ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY

## Abstract

In an embodiment, set forth by way of example and not limitation, an integrated circuit includes charge pump circuitry formed on an integrated circuit (IC) chip, a first protective circuit formed on the integrated circuit chip and coupling the first output node to a first IC port, a second protective circuit formed on the integrated circuit chip and coupling the second output node to a second IC port, and a third protective circuit formed on the integrated circuit chip and coupling the power input node to a power input IC port.

## Claims

### Claim 1

An integrated circuit comprising:
charge pump circuitry formed on an integrated circuit (IC) chip and having a first output node, a second output node, a power input node, and a control input node, wherein the charge pump circuitry includes a multiplexer (MUX) having a first input coupled to a doubler stage and a second input coupled to a level shifter;
control logic formed on the integrated circuit chip and coupled to the control input node of the charge pump circuitry;
a first protective circuit formed on the integrated circuit chip and coupling the first output node to a first IC port;
a second protective circuit formed on the integrated circuit chip and coupling the second output node to a second IC port;
a resistor coupled across the first IC port and the second IC port; and
a third protective circuit formed on the integrated circuit chip and coupling the power input node to a power input IC port;
wherein the first protective circuit, the second protective circuit and the third protective circuit each include a power field effect transistor (PFET) and a resistor coupled between a gate and a source of the PFET, wherein the sources of the PFETs are coupled to the charge pump circuitry.

### Claim 2 (depends on 1)

An integrated circuit as recited in claim 1 wherein the MUX further includes a comparator having an output coupled to an input of the MUX.

### Claim 3 (depends on 1)

An integrated circuit as recited in claim 1 wherein the charge pump circuit further includes a MOSFET having a drain coupled to an output of the MUX and having a gate coupled to the control logic.

### Claim 4 (depends on 1)

An integrated circuit as recited in claim 1 wherein the charge pump circuit further includes a shunt regulator coupled to the doubler stage.

### Claim 5

A power supply charge pump and protection circuit comprising:
charge pump circuitry having a first output node, a second output node, a power input node, and a control input node, wherein the charge pump circuitry includes a multiplexer (MUX) having a first input coupled to a doubler stage and a second input coupled to a level shifter;
a first protective circuit coupling the first output node to a first port;
a second protective circuit coupling the second output node to a second port;
a resistor coupled across the first port and the second port;
a third protective circuit coupling the power input node to a power input port; and
control logic coupled to the control input node of the charge pump circuitry;
wherein the first protective circuit, the second protective circuit and the third protective circuit each include a power field effect transistor (PFET) and a resistor coupled between a gate and a source of the PFET; and
wherein the sources of the PFETs are coupled to the charge pump circuitry.

### Claim 6 (depends on 5)

A power supply charge pump and protection circuit as recited in claim 5 wherein the MUX further includes a comparator having an output coupled to an input of the MUX.

### Claim 7 (depends on 5)

A power supply charge pump and protection circuit as recited in claim 5 wherein the charge pump circuit further includes a MOSFET having a drain coupled to an output of the MUX and having a gate coupled to the control logic.

### Claim 8 (depends on 5)

A power supply charge pump and protection circuit as recited in claim 5 herein the charge pump circuit further included a shunt regulator coupled to the doubler stage.