# US 10,121,980 B2 · Thin film transistor array panel and manufacturing method of the same

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- Number: US 10,121,980 B2
- Document ID: US10121980B2
- Status: Granted
- Kind: B2
- Application number: 15/113,581
- Filed: 2016-04-08
- Published: 2017-12-28
- Granted: 2018-11-06
- Earliest claimed: 2016-03-17
- Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Inventors: Hongyuan Xu
- Web page: https://patentgrep.com/patent/US10121980B2

## CPC

- H10K 19/10: comprising field-effect transistors
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10K 10/46: Field-effect transistors, e.g. organic thin-film transistors [OTFT] (H10K10/43 takes precedence)
- H10K 10/464: {Lateral top-gate IGFETs comprising only a single gate}
- H10K 59/1213: {the pixel elements being TFTs}
- H10K 71/231: {by etching of existing layers}
- H10K 2102/103: {comprising indium oxides, e.g. ITO}
- H10K 2102/302: {of OLED structures}
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A thin film transistor array panel and a manufacturing method are disclosed herein. The thin film transistor array panel includes a data line, a first block of a source electrode, a third block of a drain electrode, and an electrode layer which are formed by a first metal layer disposed on a baseplate; a second block of the source electrode, a fourth block of the drain electrode are formed by a second metal layer which is disposed on the first metal layer. The first block and the second block overlap to combine integrally. The third block and the fourth block overlap to combine integrally. The present invention can decrease the electrical resistance of each of the source electrode and the drain electrode.

## Claims

### Claim 1

A thin film transistor array panel, comprising:
a baseplate;
a data line, being formed by a first metal layer, wherein the first metal layer is disposed on the baseplate;
a thin film transistors, the thin film transistor comprising:
a source electrode, comprising a first block and a second block, the first block and the second block overlapping to combine integrally, the first block being a portion of the first metal layer located in a first region, the second block being a portion of a second metal layer located in the first region, wherein the first region is a portion to which the source electrode corresponds, the second metal layer disposed on the first metal layer, the source electrode connects with the data line;
a drain electrode, comprising a third block and a fourth block, the third block and the fourth block overlapping to combine integrally, the third block being a portion of the first metal layer located in a second region, the fourth block being a portion of a second metal layer located in the second region, wherein the second region is a portion to which the drain electrode corresponds, the second metal layer disposed on the first metal layer;
a semiconductor layer, being overlapping on the source electrode, the drain electrode, and a gap between the source electrode and the drain electrode;
a gate electrode, being over the semiconductor;
an insulation layer, being overlapping on the data line and the semiconductor layer;
a scanning line, being disposed on the insulation layer, the scanning line connecting with the gate electrode;
a protection layer, being disposed on the scanning line and the insulation layer;
an electrode layer, being formed by the first metal layer, the electrode layer connecting with the drain electrode;
wherein the gate electrode is disposed on the insulation layer.

### Claim 2 (depends on 1)

The thin film transistor array panel according to claim 1, wherein the semiconductor layer is an organic semiconductor layer.

### Claim 3 (depends on 1)

The thin film transistor array panel according to claim 1, wherein a portion of the first metal layer to which the electrode layer corresponds is configured to carry an organic lighting material layer and a positive electrode layer.