# US 10,121,965 B1 · Resistive random access memory device containing discrete memory material portions and method of making thereof

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- Number: US 10,121,965 B1
- Document ID: US10121965B1
- Status: Granted
- Kind: B1
- Application number: 15/692,230
- Filed: 2017-08-31
- Granted: 2018-11-06
- Earliest claimed: 2017-08-31
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Tomohiro Uno; Shiori Kataoka; Yusuke Yoshida
- Web page: https://patentgrep.com/patent/US10121965B1

## CPC

- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10D 64/662: {the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/023: {by chemical vapor deposition, e.g. MOCVD, ALD}
- H10N 70/061: {Shaping switching materials}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/8265: {on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices}
- H10N 70/883: {Oxides or nitrides}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 70/8845: {Carbon or carbides}
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An alternating stack of insulating layers and electrically conductive layers is formed over a substrate. Sidewalls of the electrically conductive layers are laterally recessed to form laterally recessed regions. After formation of a conformal barrier material layer in the laterally recessed regions and on the sidewalls of the insulating layers, an amorphous precursor memory material layer is deposited in lateral cavities and over the conformal barrier material layer. An anneal process is performed to selectively crystallize portions of the amorphous precursor memory material layer in the lateral cavities into crystalline memory material portions while not crystallizing portions of the amorphous precursor memory material outside the lateral cavities. Remaining amorphous portions of the amorphous precursor memory material layer are removed selective to the crystalline memory material portions. A vertical conductive line is formed on the crystalline memory material portions. The crystalline memory material portions are formed as discrete self-aligned material portions.

## Claims

### Claim 1

A resistive memory device comprising:
an alternating stack of insulating layers and electrically conductive layers that extend along a first horizontal direction, wherein sidewalls of the electrically conductive layers are laterally recessed relative to sidewalls of the insulating layers to define laterally recessed regions;
discrete clam shaped barrier material portions located within a respective one of the laterally recessed regions and vertically spaced apart by the insulating layers;
crystalline memory material portions located at least partially in a respective one of the clam shaped barrier material portions; and
a vertical conductive line contacting the crystalline memory material portions.

### Claim 2 (depends on 1)

The resistive memory device of claim 1, wherein the crystalline memory material portions straddle a vertical plane including the sidewalls of the insulating layers.

### Claim 3 (depends on 2)

The resistive memory device of claim 2, wherein sidewalls of the vertical conductive line that contact the clam shaped barrier material portions and the crystalline memory material portions have a laterally undulating profile.

### Claim 4 (depends on 2)

The resistive memory device of claim 2, wherein the vertical conductive line contacts the sidewalls of the insulating layers and protruding portions of horizontal surfaces of the crystalline memory material portions.

### Claim 5 (depends on 1)

The resistive memory device of claim 1, wherein each of the clam shaped barrier material portions comprises:
a vertical portion contacting a respective one of the electrically conductive layers;
an upper horizontal portion contacting a respective overlying insulating layer; and
a lower horizontal portion contacting a respective underlying insulating layer,
wherein the vertical portion, the upper horizontal portion, and the lower horizontal portion contact the respective crystalline memory material portion.

### Claim 6 (depends on 5)

The resistive memory device of claim 5, wherein each of the upper horizontal portion and the lower horizontal portion has a vertical sidewall located within a vertical plane including the sidewalls of the insulating layers.

### Claim 7 (depends on 1)

The resistive memory device of claim 1, wherein the crystalline memory material portions comprise sub-stoichiometric crystalline titanium oxide having a total thickness of at least 4 nm.

### Claim 8 (depends on 7)

The resistive memory device of claim 7, wherein:
the clam shaped barrier material portions comprise amorphous silicon; and
the crystalline memory material portions comprise the sub-stoichiometric crystalline titanium oxide having a total thickness, length and width of at least 4 nm.

### Claim 9 (depends on 1)

The resistive memory device of claim 1, wherein:
the vertical conductive line comprises a conductive metallic nitride layer that contacts the crystalline memory material portions and having a laterally undulating vertical cross-sectional profile; and
the vertical conductive line further comprises a semiconductor material portion that contacts the conductive metallic nitride layer.

### Claim 10 (depends on 1)

The resistive memory device of claim 1, wherein the vertical conductive line comprises a local vertical bit line which has a pillar shape, and is disposed between a neighboring pair of dielectric pillar structures that contact the sidewalls of the insulating layers, and wherein the electrically conductive layers comprise word lines of a barrier modulated cell of a ReRAM resistive memory device.

### Claim 11 (depends on 1)

The resistive memory device of claim 1, further comprising a vertical field effect transistor underlying or overlying the vertical conductive line, wherein an active region of the vertical field effect transistor is electrically shorted to a top end or a bottom end of the vertical conductive line.

### Claim 12

A method of forming a resistive memory device, comprising:
forming an alternating stack of insulating layers and electrically conductive layers that extend along a first horizontal direction over a substrate;
forming laterally recessed regions by laterally recessing sidewalls of the electrically conductive layers relative to sidewalls of the insulating layers;
forming a conformal barrier material layer in the lateral recessed regions and on the sidewalls of the insulating layers, wherein lateral cavities are present in unfilled volumes of the laterally recessed regions;
depositing an amorphous precursor memory material layer in the lateral cavities and over the conformal barrier material layer;
selectively crystallizing portions of the amorphous precursor memory material layer in the lateral cavities into crystalline memory material portions while not crystallizing vertical portions of the amorphous precursor memory material layer on the sidewalls of the insulating layers employing an anneal process;
removing remaining amorphous portions of the amorphous precursor memory material layer selective to the crystalline memory material portions; and
forming a vertical conductive line on the crystalline memory material portions.

### Claim 13 (depends on 12)

The method of claim 12, wherein:
the amorphous precursor memory material layer is deposited employing a conformal deposition process; and
a thickness of the amorphous precursor memory material layer is at least 4 nm.

### Claim 14 (depends on 13)

The method of claim 13, wherein the remaining amorphous portions of the amorphous precursor memory material layer are removed selective to the crystalline memory material portions employing a wet etch process that provides a wet etch selectivity greater than 5 for the amorphous portions of the amorphous precursor memory material layer relative to the crystalline memory material portions.

### Claim 15 (depends on 13)

The method of claim 13, wherein the amorphous precursor memory material layer comprises amorphous titanium oxide.

### Claim 16 (depends on 15)

The method of claim 15, wherein the conformal barrier material layer comprises a material selected from amorphous carbon, diamond-like carbon (DLC), an amorphous semiconductor material, and a polycrystalline semiconductor material.

### Claim 17 (depends on 12)

The method of claim 12, further comprising isotropically etching vertical portions of the conformal barrier material layer from the sidewalls of the insulating layers, wherein remaining portions of the conformal barrier material layer in the laterally recessed regions comprise clam shaped barrier material portions that at least partially surrounds a respective one of the crystalline memory material portions.

### Claim 18 (depends on 17)

The method of claim 17, wherein the vertical conductive line is formed on top surfaces and bottom surfaces of laterally protruding portions of the crystalline memory material portions that protrude out of the clam shaped barrier material portions and on the sidewalls of the insulating layers.

### Claim 19 (depends on 12)

The method of claim 12, wherein:
the vertical conductive line comprises a semiconductor material portion and a conductive metallic nitride layer that contacts the crystalline memory material portions and having a laterally undulating vertical cross-sectional profile; and
the vertical conductive line has a pillar shape, and is disposed between a neighboring pair of dielectric pillar structures that contact the sidewalls of the insulating layers.

### Claim 20 (depends on 12)

The method of claim 12, further comprising forming a vertical field effect transistor under, or over, the vertical conductive line, wherein an active region of the vertical field effect transistor is electrically shorted to a top end or a bottom end of the vertical conductive line.