# US 10,121,964 B2 · Integrated magnetic random access memory with logic device

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- Number: US 10,121,964 B2
- Document ID: US10121964B2
- Status: Granted
- Kind: B2
- Application number: 14/862,180
- Filed: 2015-09-23
- Published: 2017-03-23
- Granted: 2018-11-06
- Earliest claimed: 2015-09-23
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Inventors: Juan Boon Tan; Yi Jiang; Daxiang Wang; Fan Zhang; Francis Poh; Danny Pak-Chum Shum
- Web page: https://patentgrep.com/patent/US10121964B2

## CPC

- H10N 50/01: Manufacture or treatment
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/10: Magnetoresistive devices
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Integrating magnetic random access memory with logic is disclosed. The magnetic tunnel junction stack of a magnetic memory cell is disposed within a dielectric layer which serves as a via level of an interlevel dielectric layer with a metal level above the via level. An integration scheme for forming dual damascene structures for interconnects can be formed to logic and memory cells easily.

## Claims

### Claim 1

A method of forming a device comprising:
providing a substrate defined with at least first and second regions, the first region comprises a memory region for magnetic random access memories (MRAMs) and the second region comprises a logic region, wherein the substrate is prepared with
front-end-of-line (FEOL) components on the substrate in the first and second regions, and
a lower back-end-of-line (BEOL) dielectric layer disposed over the substrate covering the FEOL components, the lower BEOL dielectric layer comprises
L interconnect dielectric (ILD) level, where L is a whole number greater than or equal to 1 but less than x, where x is the total number of ILD levels for the device, and
wherein an ith ILD level of the device comprises a via level Vi−1 dielectric below a metal level Mi dielectric, where i is from 1 to x, and the via level Vi−1 dielectric includes contacts and the metal level Mi dielectric includes metal lines;
forming a lower dielectric liner on a metal level ML dielectric, which is a top of the lower BEOL dielectric layer in the first and second regions;
forming a magnetic tunnel junction (MTJ) stack of a magnetic random access memory (MRAM) cell in the first region of the substrate on the lower dielectric liner, the MTJ stack includes a MTJ disposed between top and bottom electrodes, wherein the MTJ stack includes a lower MTJ portion which includes the bottom electrode and an upper MTJ portion which includes the top electrode, the bottom electrode is electrically coupled to a lower metal line in the metal level ML dielectric below through an opening in the lower dielectric liner, wherein the upper MTJ portion and the lower MTJ portion are formed in separate patterning processes, wherein the MTJ stack includes a dielectric liner disposed on the MTJ stack;
forming a dielectric layer on the substrate in the first and second regions, the dielectric layer is disposed on the MTJ stack including the dielectric liner and on the lower dielectric liner, the dielectric layer serves as a via level Vi dielectric above the metal level ML dielectric;
forming an upper dielectric liner on the dielectric layer in the first and second regions, wherein the upper dielectric liner is patterned to form first and second openings corresponding to first and second vias of first and second dual damascene structures in the first and second regions;
forming a metal level dielectric layer on the upper dielectric liner with the first and second openings in the first and second regions, wherein the metal level dielectric layer serves as a metal level Mi+1 dielectric;
performing a first etch, wherein the first etch
patterns the metal level dielectric layer, which serves as the metal level Mi+1 dielectric, to form first and second trenches, and
patterns the dielectric layer, which serves as the via level Vi dielectric, using the upper dielectric liner as an etch mask to form the first and second vias, wherein the first via stops at the dielectric liner and the second via stops at the lower dielectric liner; and
performing a second etch, wherein the second etch
patterns the dielectric liner at the first via to expose the top electrode of the MTJ stack, and the lower dielectric liner at the second via to expose a logic metal line in the metal level ML dielectric.

### Claim 2 (depends on 1)

The method of claim 1 wherein:
the first and second dual damascene structures are filled with metal to form first and second metal lines with first and second via contacts in the first and second dual damascene structures; and
the first metal line of the first dual damascene structure serves as a top metal line.

### Claim 3 (depends on 1)

The method of claim 1 wherein forming the MTJ stack comprises:
forming various layers of the MTJ stack on the lower dielectric liner in the first and second regions;
patterning layers of the upper MTJ portion to form the upper MTJ portion in the first region using a first patterning process;
forming the dielectric liner on the substrate, the dielectric liner lines the upper MTJ portion and a top layer of the lower MTJ portion; and
patterning layers of the lower MTJ portion to form the MTJ stack in the first region using a second patterning process with the dielectric liner lining the MTJ stack.

### Claim 4 (depends on 3)

The method of claim 3 wherein the second patterning process forms the lower MTJ portion which is larger than the upper MTJ portion.

### Claim 5 (depends on 4)

The method of claim 4 wherein:
the layers of the lower MTJ portion comprises
the bottom electrode,
a first fixed layer, and
a first tunneling barrier layer; and
the layers of the upper MTJ portion comprises
a free layer, and
the top electrode.

### Claim 6 (depends on 5)

The method of claim 5 wherein the layers of the upper portion comprise a second tunneling barrier layer between the free layer and the top electrode.

### Claim 7 (depends on 6)

The method of claim 6 wherein the dielectric layer has a planar top surface.

### Claim 8 (depends on 7)

The method of claim 7 comprising planarizing the dielectric layer by chemical mechanical polishing to form the planar top surface.

### Claim 9 (depends on 1)

The method of claim 1 wherein the lower dielectric liner comprises:
a first lower dielectric liner on the top of the lower BEOL dielectric layer; and
a second lower dielectric liner on the first lower dielectric liner.

### Claim 10 (depends on 9)

The method of claim 9 wherein the first lower dielectric liner on the top of the lower BEOL dielectric layer comprises a low k dielectric layer and serves as an etch stop layer.

### Claim 11

A method of forming a device comprising:
providing a substrate defined with at least first and second regions, the first region comprises a memory region for magnetic random access memories (MRAMs) and the second region comprises a logic region, wherein the substrate is prepared with
front-end-of-line (FEOL) components on the substrate in the first and second regions, and
a lower back-end-of-line (BEOL) dielectric layer disposed over the substrate covering the FEOL components, the lower BEOL dielectric layer comprises
L interconnect dielectric (ILD) level, where L is a whole number greater than or equal to 1 but less than x, where x is the total number of ILD levels for the device, and
wherein an ith ILD level of the device comprises a via level Vi−1 dielectric below a metal level Mi dielectric, where i is from 1 to x, and the via level Vi−1 dielectric includes contacts and the metal level Mi dielectric includes metal lines;
forming a lower dielectric liner on a metal level ML dielectric, which is a top of the lower BEOL dielectric layer in the first and second regions, wherein the lower dielectric liner comprises
a first lower dielectric liner on the top of the lower BEOL dielectric layer, and
a second lower dielectric liner on the first lower dielectric liner;
forming a magnetic tunnel junction (MTJ) stack of a magnetic random access memory (MRAM) cell in the first region of the substrate on the lower dielectric liner, the MTJ stack includes a MTJ disposed between top and bottom electrodes, wherein the MTJ stack includes a lower MTJ portion which includes the bottom electrode and an upper MTJ portion which includes the top electrode, the bottom electrode is electrically coupled to a lower metal line in the metal level ML dielectric below through an opening in the lower dielectric liner, wherein the upper MTJ portion and the lower MTJ portion are formed in separate patterning processes, wherein the MTJ stack includes a dielectric liner disposed on the MTJ stack;
forming a dielectric layer on the substrate in the first and second regions, the dielectric layer is disposed on the MTJ stack including the dielectric liner and on the lower dielectric liner, the dielectric layer serves as a via level Vi dielectric above the metal level ML dielectric;
forming an upper dielectric liner on the dielectric layer in the first and second regions, wherein the upper dielectric liner is patterned to form first and second openings corresponding to first and second vias of first and second dual damascene structures in the first and second regions, wherein forming the first and second dual damascene structures comprises
etching the metal level Mi+1 dielectric and the via level Vi dielectric to form the first and second vias, wherein the first via stops at the dielectric liner and the second via stops at the first lower dielectric liner; and
etching to remove exposed dielectric liner in the first region to expose the top electrode and exposed first lower dielectric liner in the second region to expose a logic metal line in the metal level ML dielectric;
forming a metal level dielectric layer on the upper dielectric liner with the first and second openings in the first and second regions, wherein the metal level dielectric layer serves as a metal level Mi+1 dielectric;
performing a first etch, wherein the first etch
patterns the metal level dielectric layer, which serves as the metal level Mi+1 dielectric, to form first and second trenches, and
patterns the dielectric layer, which serves as the via level Vi dielectric, using the upper dielectric liner as an etch mask to form the first and second vias, wherein the first via stops at the dielectric liner and the second via stops at the lower dielectric liner; and
performing a second etch, wherein the second etch
patterns the dielectric liner at the first via to expose the top electrode of the MTJ stack, and the lower dielectric liner at the second via to expose a logic metal line in the metal level ML dielectric.

### Claim 12 (depends on 11)

The method of claim 11 wherein:
etching the metal level dielectric-layer and the dielectric layer comprises a first etch; and
etching the exposed dielectric liner and the exposed first lower dielectric liner comprises a second etch.

### Claim 13 (depends on 1)

The method of claim 1 wherein metal lines of metal level ML are defined based on 1× design rule and metal lines of metal level Mi+1 are defined based on 2× design rule.

### Claim 14 (depends on 1)

The method of claim 1 wherein:
the dielectric liner lines top and sidewalls of the upper MTJ portion and top of the lower MTJ portion.

### Claim 15

A method for forming a device comprising:
providing a substrate defined with at least first and second regions, the first region comprises a memory region for magnetic random access memories (MRAMs) and the second region comprises a logic region, wherein the substrate is prepared with
front-end-of-line (FEOL) components on the substrate in the first and second regions, and
a lower back-end-of-line (BEOL) dielectric layer disposed over the substrate covering the FEOL components, the lower BEOL dielectric layer comprises
L interconnect dielectric (ILD) level, where L is a whole number greater than or equal to 1 but less than x, where x is the total number of ILD levels for the device, and
wherein an ith ILD level of the device comprises a via level Vi−1 dielectric below a metal level Mi dielectric, where i is from 1 to x, and the via level dielectric includes contacts and the metal level Mi dielectric includes metal lines;
forming a lower dielectric liner on a metal level ML dielectric, which is a top of the lower BEOL dielectric layer in the first and second regions;
forming a dielectric layer which serves as a via level Vi above the metal level ML dielectric, wherein the dielectric layer is prepared with a dielectric liner disposed over a magnetic tunnel junction (MTJ) stack which includes a MTJ between top and bottom electrodes, wherein the bottom electrode of the MTJ stack is electrically coupled to a lower metal line in the metal level ML dielectric below through an opening in the lower dielectric liner;
forming a metal level dielectric layer over the via level dielectric layer, the metal level dielectric layer serves as a metal level Mi+1 dielectric;
performing a first etch to form a first dual damascene structure in the first region, wherein the first etch
patterns the metal level Mi+1 dielectric layer, which serves as the metal level Mi+1 dielectric, to form a first trench, and
patterns the dielectric layer, which serves as the via level Vi dielectric, to form a first via, wherein the first via stops at the dielectric liner; and
performing a second etch on the dielectric liner at the first via to expose the top electrode of the MTJ stack.

### Claim 16 (depends on 15)

The method of claim 15 wherein the MTJ stack comprises a lower MTJ portion and an upper MTJ portion, wherein the lower MTJ portion is larger than the upper MTJ portion.

### Claim 17 (depends on 16)

The method of claim 16 wherein:
layers of the lower MTJ portion comprises
the bottom electrode,
a first fixed layer, and
a first tunneling layer; and
layers of the upper MTJ portion comprises
a free layer, and
the top electrode.

### Claim 18

A device comprising:
a substrate defined with at least first and second regions, the first region comprises a memory region for magnetic random access memories (MRAMs) and the second region comprises a logic region;
front-end-of-line (FEOL) components provided on the substrate in the first and second regions;
a lower back-end-of-line (BEOL) dielectric layer disposed over the substrate covering the FEOL components, the lower BEOL dielectric layer comprises
L interconnect dielectric (ILD) level, where L is a whole number greater than or equal to 1 but less than x, where x is the total number of ILD levels for the device, and
wherein an ith ILD level of the device comprises a via level Vi−1 dielectric below a metal level Mi dielectric, where i is from 1 to x, and the via level Vi−1 dielectric includes contacts and the metal level Mi dielectric includes metal lines;
a lower dielectric liner disposed on a metal level ML dielectric, which is a top of the lower BEOL dielectric layer in the first and second regions;
a dielectric layer disposed on the substrate in the first and second regions, the dielectric layer includes a lower portion and an upper portion, and wherein the dielectric layer includes a magnetic tunnel junction (MTJ) stack of a MRAM cell disposed on the lower dielectric liner in the first region of the substrate, the MTJ stack includes a MTJ disposed between top and bottom electrodes;
a MTJ dielectric liner disposed over a top surface of the MTJ stack, wherein the MTJ stack with the MTJ dielectric liner is disposed in the lower portion of the dielectric layer, and wherein the upper portion of the dielectric layer is disposed between the top of the MTJ dielectric liner and an upper dielectric liner, the dielectric layer serves as a via level VL dielectric above the metal level ML dielectric, and wherein the upper dielectric liner is disposed on the VL dielectric layer in the first and second regions, wherein the upper dielectric liner includes via openings in the first and second regions;
a metal level dielectric layer disposed on the upper dielectric liner in the first and second regions, wherein the metal level dielectric layer serves as a metal level ML+1 dielectric; and
first and second via contacts disposed in the VL dielectric layer in the first and second regions, wherein
the first via contact is disposed in a first via from the top of the VL dielectric layer to the MTJ stack through the MTJ dielectric liner, the first via contact is coupled to the MTJ stack which is connected to a first ML metal line, and a first ML+1 metal line in the metal level ML+1 dielectric, and
the second via contact is disposed in a second via from the top of the VL dielectric layer to a second ML metal line in the metal level ML dielectric through the lower dielectric liner, the second via is a single continuous via, the second via contact is coupled to the second ML metal line and a second ML+1 metal line in the metal level ML+1 dielectric.

### Claim 19 (depends on 18)

The device of claim 18 wherein the MTJ stack comprises a lower MTJ portion and an upper MTJ portion, wherein the lower MTJ portion has a length that is larger than a length of the upper MTJ portion.

### Claim 20 (depends on 19)

The device of claim 19 wherein:
layers of the lower MTJ portion comprises
the bottom electrode,
a first fixed layer, and
a first tunneling layer; and
layers of the upper MTJ portion comprises
a free layer, and
the top electrode.