# US 10,121,962 B1 · Method for fabricating magnetic solid state devices

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- Number: US 10,121,962 B1
- Document ID: US10121962B1
- Status: Granted
- Kind: B1
- Application number: 15/589,626
- Filed: 2017-05-08
- Published: 2018-11-08
- Granted: 2018-11-06
- Earliest claimed: 2017-05-08
- Assignees: Board of Regents, The University of Texas System
- Applicants: The University of Texas System Board of Regents
- Inventors: Leonard Franklin Register, II; Bahniman Ghosh; Rik Dey; Sanjay Kumar Banerjee
- Web page: https://patentgrep.com/patent/US10121962B1

## CPC

- H10N 50/85: Materials of the active region
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B 61/20: {comprising components having three or more electrodes, e.g. transistors}
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A magnetic solid state device is disclosed. The magnetic solid state device includes a substrate and a topological insulator deposited on top of the substrate. The magnetic solid state device also includes a first perpendicular magnetic anisotropy (PMA) bit having a reference PMA layer located on the topological insulator, and a second PMA bit having a free PMA layer located on the topological insulator. A gate contact is utilized to receive various predetermined voltages for controlling the Ruderman-Kittel-Kasuya-Yosida (RKKY) interactions between the reference PMA layer in the first PMA bit and the free PMA layer in the second PMA bit.

## Claims

### Claim 1

A method for fabricating a magnetic memory, said method comprising:
forming a stack of second oxide layer/second perpendicular magnetic anisotropy (PMA) layer/first oxide/first PMA layer/topological insulator on a substrate;
forming a plurality of PMA bits on said substrate;
removing said second PMA layer and said second oxide layer on one of said PMA bits to form a reference PMA bit;
depositing a gate oxide layer on said PMA bits and non-PMA bit regions;
depositing a gate contact on a region located between said first PMA bit and said second PMA bit; and
depositing a metal connector on said second PMA bit to form a storage PMA bit.

### Claim 2 (depends on 1)

The method of claim 1, wherein said substrate is made of silicon.

### Claim 3 (depends on 1)

The method of claim 1, wherein said topological insulator is made of Bi2Se3.

### Claim 4 (depends on 1)

The method of claim 1, wherein said topological insulator is made of Bi2Te3.

### Claim 5 (depends on 1)

The method of claim 1, wherein said first oxide and said second oxide are made of magnesium oxide.

### Claim 6 (depends on 1)

The method of claim 1, wherein said PMA free layer and said second PMA reference layer are made of ferromagnetic material.