# US 10,121,959 B1 · FDSOI STT-MRAM design

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,121,959 B1
- Document ID: US10121959B1
- Status: Granted
- Kind: B1
- Application number: 15/625,272
- Filed: 2017-06-16
- Granted: 2018-11-06
- Earliest claimed: 2017-06-16
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Inventors: Yinjie Ding; Eng Huat Toh; Kangho Lee; Elgin Kiok Boone Quek
- Web page: https://patentgrep.com/patent/US10121959B1

## CPC

- H10N 50/80: Constructional details
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 11/1675: {Writing or programming circuits or methods}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- G11C 11/1657: {Word-line or row circuits}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method of forming a segmented FDSOI STT-MRAM using dummy WL blocks and the resulting device are provided. Embodiments include forming a plurality of FDSOI STT-MRAM active WL blocks laterally separated across a memory array; forming a FDSOI STT-MRAM dummy WL block parallel to and on opposite sides of each active WL block; forming a plurality of SL structures laterally separated across the memory array; forming a plurality of BL structures laterally separated across the memory array; and connecting the plurality of SL and BL structures to the plurality of active WL blocks.

## Claims

### Claim 1

A method comprising:
forming a plurality of fully depleted silicon-on-insulator spin-transfer torque magnetoresistive random-access memory (FDSOI STT-MRAM) active word line (WL) blocks laterally separated across a memory array, each active WL block formed by:
forming a n-type well (NW);
forming a n-type ground plane (GP-N) layer over the NW;
forming a buried oxide (BOX) layer over the GP-N layer;
forming a silicon (Si) layer over the BOX layer;
forming two pairs of two gates laterally separated over the Si layer;
forming a shallow trench isolation (STI) region through the Si, BOX, and GP-N layers and a portion of the NW on opposite sides of each pair of gates;
forming a n-type lightly dope drain (nLDD) in the Si layer on opposite sides and under a portion of each gate; and
forming a n-type raised source/drain (nRSD) over each nLDD adjacent to and on opposite sides of each gate;
forming a FDSOI STT-MRAM dummy WL block parallel to and on opposite sides of each active WL block;
forming a plurality of source line (SL) structures laterally separated across the memory array;
forming a plurality of bit line (BL) structures laterally separated across the memory array; and
connecting the plurality of SL and BL structures to the plurality of active WLblocks.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising:
selecting one active WL block for a write function;
applying forward body bias (FBB) to the selected active WL block; and
applying zero or reverse body bias (RBB) to all unselected active WL blocks.

### Claim 3 (depends on 1)

The method according to claim 1, comprising forming each dummy WL block by:
forming a p-type well (PW);
forming a p-type ground plane (GP-P) layer over the PW;
forming the BOX layer over the GP-P layer;
forming the Si layer over the BOX layer;
forming gates laterally separated over the Si layer;
forming a STI region through the Si, BOX, and GP-P layers and a portion of the PW on opposite sides of the gates;
forming a nLDD in the Si layer on opposite sides and under a portion of each gate; and
forming a nRSD above each nLDD adjacent to and on opposite sides of each gate.

### Claim 4 (depends on 3)

The method according to claim 3, comprising utilizing each gate of an active WL block as an active WL and each gate of a dummy WL block as a dummy WL.

### Claim 5 (depends on 3)

The method according to claim 3, comprising connecting a SL structure to the plurality of active blocks by:
forming a SL contact over a nRSD between each pair of gates of each active WL block; and
connecting the SL structure to the SL contacts.

### Claim 6 (depends on 3)

The method according to claim 3, comprising connecting a BL structure to the plurality of active WL blocks by:
forming a metal/via stack or contact (CT) over each nRSD on opposite sides of each pair of gates of each active WL block;
forming a landing pad over each CT;
forming a magnetic tunneling junction (MTJ) stack over each landing pad; and
connecting the BL structure to the MTJ stacks.

### Claim 7 (depends on 6)

The method according to claim 6, comprising connecting a SL and a BL structure to the plurality of dummy WL blocks by:
forming a SL contact over a nRSD between a pair of gates of each dummy WL block;
forming a CT over each nRSD on opposite sides of a pair of gates of each dummy WL block;
connecting the ST structure to the SL contacts; and
connecting the BL structure to the MTJ stacks.

### Claim 8

A device comprising:
a plurality of fully depleted silicon-on-insulator spin-transfer torque magnetoresistive random-access memory (FDSOI STT-MRAM) active word line (WL) blocks laterally separated across a memory array, wherein each active WL block comprises:
a n-type well (NW);
a n-type ground plane (GP-N) layer over the NW;
a buried oxide (BOX) layer over the GP-N layer;
a silicon (Si) layer over the BOX layer;
two pairs of two gates laterally separated over the Si layer;
a shallow trench isolation (STI) region through the Si layer, BOX, and GP-N layers and a portion of the NW on opposite sides of each pair of gates;
a n-type lightly dope drain (nLDD) in the Si layer on opposite sides and under a portion of each gate; and
a n-type raised source/drain (nRSD) over each nLDD adjacent to and on opposite sides of each gate;
a FDSOI STT-MRAM dummy WL block parallel to and on opposite sides of each active WL block;
a plurality of source line (SL) structures laterally separated across the memory array; and
a plurality of bit line (BL) structures laterally separated across the memory array,
wherein each SL and BL structure is connected to the plurality of active WL blocks.

### Claim 9 (depends on 8)

The device according to claim 8, wherein one active WL block selected for a write function allows an application of forward body bias (FBB) and all unselected active WL blocks allow an application of zero or reverse body bias (RBB).

### Claim 10 (depends on 8)

The device according to claim 8, wherein each dummy WL block comprises:
a p-type well (PW);
a p-type ground plane (GP-P) layer over the PW;
the BOX layer over the GP-P layer;
the Si layer over the BOX layer;
a pair of the gates laterally separated over the Si layer;
the STI region through the Si, BOX, and GP-P layers and a portion of the PW on opposite sides of the gates;
the nLDD in the Si layer on opposite sides and under a portion of each gate; and
the nRSD above each nLDD adjacent to and on opposite sides of each gate.

### Claim 11 (depends on 10)

The device according to claim 10, wherein each gate of an active WL block is utilized as an active WL and each gate of a dummy WL block is utilized as a dummy WL.

### Claim 12 (depends on 10)

The device according to claim 10, wherein the connection between a SL structure and the plurality of active blocks comprises:
a SL contact over each nRSD between each pair of gates of each active WL block.

### Claim 13 (depends on 10)

The device according to claim 10, wherein the connection between a BL structure and the plurality of active blocks comprises:
a metal/via stack or contact (CT) over each nRSD on opposite sides of each pair of gates of each active WL block;
a landing pad over each CT; and
a magnetic tunneling junction (MTJ) stack over each landing pad.

### Claim 14 (depends on 13)

The device according to claim 13, wherein the connection between a SL structure and the plurality of dummy WL blocks and the connection between a BL structure and the plurality of dummy WL blocks respectively comprise:
a SL contact over each nRSD between a pair of gates of each dummy WL block; and
a CT over each nRSD on opposite sides of a pair of gates of each dummy WL block.

### Claim 15 (depends on 8)

The device according to claim 8, wherein the plurality of active and dummy WL blocks comprise a one transistor and one MTJ (1T1MTJ), a two transistors and one MTJ (2T1MTJ), a SL//BL, or a local SL cell structure.

### Claim 16

A method comprising:
forming a plurality of fully depleted silicon-on-insulator spin-transfer torque magnetoresistive random-access memory (FDSOI STT-MRAM) active word line (WL) blocks laterally separated across a memory array, each active WL block formed by:
forming a n-type well (NW);
forming a n-type ground plane (GP-N) layer over the NW;
forming a buried oxide (BOX) layer over the GP-N layer;
forming a silicon (Si) layer over the BOX layer;
forming two pairs of two gates laterally separated over the Si layer;
forming a shallow trench isolation (STI) region through the Si layer, BOX, and GP-N layers and a portion of the NW on opposite sides of each pair of gates;
forming a n-type lightly dope drain (nLDD) in the Si layer on opposite sides and under a portion of each gate; and
forming a n-type raised source/drain (nRSD) over each nLDD adjacent to and on opposite sides of each gate;
forming a FDSOI STT-MRAM dummy WL block parallel to and on opposite sides of each active WL block;
forming a plurality of source line (SL) structures laterally separated across the memory array, perpendicular to the active and dummy WL blocks;
forming a plurality of bit line (BL) structures laterally separated across the memory array, parallel to the plurality of SL structures and perpendicular to the active and dummy WL blocks;
connecting the plurality of SL and BL structures to the plurality of active and dummy WL blocks;
selecting one active WL block for a write function;
applying forward body bias (FBB) to the selected active WL block; and
applying zero or reverse body bias (RBB) to all unselected active WL blocks.

### Claim 17 (depends on 16)

The method according to claim 16, comprising forming each dummy WL block by:
forming a p-type well (PW);
forming a p-type ground plane (GP-P) layer over the PW;
forming the BOX layer over the GP-P layer;
forming the Si layer over the BOX layer;
forming a pair of the gates laterally separated over the Si layer;
forming the STI region through the Si layer, BOX, and GP-P layers and a portion of the PW on opposite sides of the gates;
forming the nLDD in the Si layer on opposite sides and under a portion of each gate; and
forming the nRSD above each nLDD adjacent to and on opposite sides of each gate.