# US 10,121,933 B2 · Semiconductor device and the manufacturing method thereof

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- Number: US 10,121,933 B2
- Document ID: US10121933B2
- Status: Granted
- Kind: B2
- Application number: 15/468,688
- Filed: 2017-03-24
- Published: 2017-09-28
- Granted: 2018-11-06
- Earliest claimed: 2016-03-25
- Assignees: Epistar Corporation
- Applicants: Epistar Corporation
- Inventors: Meng Yang Chen; Rong Ren Lee; Shih Chang Lee
- Web page: https://patentgrep.com/patent/US10121933B2

## CPC

- H10H 20/013: {having light-emitting regions comprising only Group III-V materials}
- H10H 20/811: having quantum effect structures or superlattices, e.g. tunnel junctions
- H10H 20/815: having stress relaxation structures, e.g. buffer layers
- H10H 20/824: comprising only Group III-V materials, e.g. GaP
- H10H 20/82: Roughened surfaces, e.g. at the interface between epitaxial layers
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS

## Abstract

The present disclosure discloses a method forming a semiconductor light-emitting unit, comprising the steps of providing a semiconductor substrate; epitaxially growing a reaction layer on the semiconductor substrate; and epitaxially growing a buffer layer on the reaction layer; wherein the buffer layer and the semiconductor substrate are lattice-mismatched, and a dislocation density of the buffer layer is smaller than smaller than 1*109 cm−2.

## Claims

### Claim 1

A method forming a semiconductor light-emitting unit, comprising the steps of:
providing a semiconductor substrate;
epitaxially growing a reaction layer on the semiconductor substrate; and
epitaxially growing a buffer layer on the reaction layer,
wherein the buffer layer and the semiconductor substrate are lattice-mismatched, and a dislocation density of the buffer layer is smaller than 1*109 cm−2, and
wherein the buffer layer comprises GaP or InP.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising a step of forming a pattern surface by patterning a surface of the reaction layer, and epitaxially growing a light-emitting stack on the buffer layer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein a difference of lattice constant between the buffer layer and the semiconductor substrate is larger than 0.1Å.

### Claim 4 (depends on 1)

The method according to claim 1, wherein an X-ray diffraction (XRD) chart of the buffer layer comprises a Full Width at Half Maximum (FWHM) smaller than 500 arcsec.

### Claim 5 (depends on 1)

The method according to claim 1, wherein a bandgap of the buffer layer is smaller than 1.4eV.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the semiconductor substrate comprises IIIA arsenide.

### Claim 7 (depends on 6)

The method according to claim 6, wherein semiconductor substrate comprises GaAs.

### Claim 8 (depends on 2)

The method according to claim 2, wherein the patterned surface comprises a regular pattern.

### Claim 9 (depends on 8)

The method according to claim 8, wherein the regular pattern comprises multiple cylinders and a distance between any two of the neighboring cylinders is the same.

### Claim 10 (depends on 2)

The method according to claim 2, wherein the patterned surface comprises an irregular pattern.

### Claim 11 (depends on 1)

The method according to claim 1, wherein the reaction layer comprises III-V semiconductor compound.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the reaction layer comprises ternary III-V semiconductor compound or quaternary III-V semiconductor compound.

### Claim 13 (depends on 1)

The method according to claim 1, wherein a thickness of the reaction layer is between 0.1 μm and 10 μm.

### Claim 14 (depends on 2)

The method according to claim 2, wherein the light-emitting stack emits a light with a peak wavelength between 1000 nm and 1500 nm.

### Claim 15 (depends on 2)

The method according to claim 2, wherein the light-emitting stack comprises a first semiconductor layer, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and wherein the active layer comprises (AlxGa1−x)yIn1−yAs, 0<x<1, 0<y<1.

### Claim 16 (depends on 15)

The method according to claim 15, wherein both of the active layer and the semiconductor substrate comprise Ga or As.

### Claim 17 (depends on 15)

The method according to claim 15, wherein the first semiconductor layer and the second semiconductor layer comprises InP or InbAl1−bAs, 0<b<1.

### Claim 18 (depends on 2)

The method according to claim 2, further comprising a step of forming a protective layer on the reaction layer, wherein the reaction layer comprises Al.

### Claim 19 (depends on 18)

The method according to claim 18, further comprising a step of removing the protective layer, wherein the protective layer is devoid of Al.