# US 10,121,928 B2 · Semiconductor photomultiplier and a process of manufacturing a photomultiplier microcell

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- Number: US 10,121,928 B2
- Document ID: US10121928B2
- Status: Granted
- Kind: B2
- Application number: 14/321,487
- Filed: 2014-07-01
- Published: 2016-01-07
- Granted: 2018-11-06
- Earliest claimed: 2014-07-01
- Assignees: SensL Technologies Ltd.
- Applicants: SensL Technologies Ltd.
- Inventors: Kevin O'Neill; Liam Wall; John Carlton Jackson
- Web page: https://patentgrep.com/patent/US10121928B2

## CPC

- H10F 30/225: the potential barrier working in avalanche mode, e.g. avalanche photodiodes
- H10F 39/024: {of coatings or optical elements}
- H10F 39/805: {Coatings}
- H10F 77/413: {directly associated or integrated with the devices, e.g. back reflectors (directly associated or integrated with photovoltaic cells H10F77/42)}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

The present disclosure relates to a process of manufacturing a photomultiplier microcell. The process comprises providing an insulating layer over an active region; and implanting a dopant through the insulating layer to form a photosensitive diode in the active region. The insulating layer once formed is retained over the active region throughout the manufacturing process.

## Claims

### Claim 1

A process of manufacturing a photomultiplier microcell;
the process comprising;
forming an insulating layer over an active region, wherein the insulating layer facilitates transmission of light through the insulating layer into the active region;
implanting a dopant through the insulating layer to form a photosensitive diode in the active region, wherein the photosensitive diode comprises an avalanche photo diode (APD) formed on a semiconductor substrate;
forming an etch stop layer over the insulating layer and creating electrical connections to the photosensitive diode through the insulation layer; and
etching an optical pathway to the etch stop layer, wherein the insulating layer once formed is retained directly over the photosensitive diode throughout the manufacturing process such that the photosensitive diode receives light at least through the insulating layer via the optical pathway, wherein a first refractive index of the insulating layer is mathematically related to a second refractive index associated with the optical pathway.

### Claim 2 (depends on 1)

A process of claim 1, wherein an epitaxial layer is provided intermediate the insulating layer and a substrate.

### Claim 3 (depends on 2)

A process of claim 2, wherein the insulating layer is formed directly on the epitaxial layer.

### Claim 4 (depends on 2)

A process of claim 2, wherein in the epitaxial layer comprises a PN junction with specific implanted dopants such that the photosensitive diode is a Geiger Mode APD.

### Claim 5 (depends on 1)

A process of claim 1, wherein the insulating layer is formed directly on a surface of a substrate.

### Claim 6 (depends on 1)

A process of claim 1, wherein the substrate is highly doped for providing a low resistivity bulk region.

### Claim 7 (depends on 1)

A process of claim 1, wherein the insulating layer comprises an oxide material.

### Claim 8 (depends on 1)

A process of claim 1, wherein an anti-reflective coating is provided on the insulating layer.

### Claim 9 (depends on 8)

A process of claim 8, wherein the anti-reflective coating comprises a combination of a plurality of materials.

### Claim 10 (depends on 9)

A process of claim 9, wherein the anti-reflective coating comprises a combination of silicon oxide (SiO2) and silicon nitride (Si3N4).

### Claim 11 (depends on 9)

A process of claim 9, wherein the anti-reflective coating comprises multiple layers of two or more materials.

### Claim 12 (depends on 11)

A process of claim 11, wherein the anti-reflective coating comprises a layer of 144 nm thick SiO2 and a layer of 45 nm thick Si3N4.

### Claim 13 (depends on 11)

A process of claim 11, wherein the anti-reflective coating comprises a first layer of 144 nm thick SiO2, a layer of 45 nm thick Si3N4 and a second layer of 144 nm thick SiO2.

### Claim 14 (depends on 11)

A process of claim 11, wherein the anti-reflective coating comprises a layer of 36 nm thick SiO and a layer of 16 nm thick SiN.

### Claim 15 (depends on 8)

A process of claim 8, wherein the anti-reflective coating has a thickness of a ¼ of a wavelength of interest divided by the refractive index of the anti-reflective coating.

### Claim 16 (depends on 15)

A process of claim 15, wherein the refractive index of anti-reflective coating is between the refractive index of silicon and the refractive index of the insulating layer.

### Claim 17 (depends on 16)

A process of claim 16, wherein the refractive index of the anti-reflective coating is the geometric mean of the refractive index of silicon and the refractive index of the insulating layer.

### Claim 18 (depends on 8)

A process of claim 8, wherein the anti-reflective coating comprises silicon oxide.

### Claim 19 (depends on 8)

A process of claim 8; wherein the anti-reflective coating has a thickness in the range of 10 nm to 50 nm.

### Claim 20 (depends on 19)

A process of claim 19, wherein the anti-reflective coating comprises SiO with a thickness of 36 nm and SiN with a thickness in the range of 10 nm-45 nm.

### Claim 21 (depends on 1)

A process of claim 1, wherein the optical pathway is formed by etching a trench into a dielectric layer.

### Claim 22 (depends on 21)

A process of claim 21, wherein the etch stop is removed after the trench has been formed.

### Claim 23 (depends on 1)

A process of claim 1, further comprising forming a quench resistor which is associated with the photosensitive diode.

### Claim 24 (depends on 1)

A process of claim 1, wherein the dopant is applied using ion implantation.

### Claim 25 (depends on 1)

A process of claim 1, wherein the dopant is a P type material.

### Claim 26 (depends on 1)

A process of claim 1, wherein the dopant is an N type material.

### Claim 27 (depends on 1)

A process of claim 1, wherein the insulating layer has a thickness in the range of 10 nm to 50 nm.

### Claim 28 (depends on 1)

A process of claim 1, wherein the insulating layer comprises silicon nitride.

### Claim 29 (depends on 1)

A process of claim 1, wherein the photomultiplier microcell is a silicon photomultiplier microcell.