# US 10,121,909 B2 · Power semiconductor rectifier with controllable on-state voltage > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,909 B2 - Document ID: US10121909B2 - Status: Granted - Kind: B2 - Application number: 15/066,561 - Filed: 2016-03-10 - Published: 2016-09-15 - Granted: 2018-11-06 - Earliest claimed: 2015-03-10 - Assignees: ABB Schweiz AG - Applicants: ABB Technology AG - Inventors: Renato Minamisawa; Andrei Mihaila; Vinoth Sundaramoorthy - Web page: https://patentgrep.com/patent/US10121909B2 ## CPC - H10D 8/60: Schottky-barrier diodes - H10D 8/051: {of Schottky diodes} - H10D 62/124: {Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions} - H10D 62/129: {Cathode regions of diodes} - H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge - H10D 62/8325: {Silicon carbide} - H10D 64/0115: {to silicon carbide} - H10D 64/0123: {to silicon carbide} - H10D 64/23: Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes - H10P 14/3408: {Silicon carbide} - H10P 14/3411: {Silicon, silicon germanium or germanium} - H10P 14/40: of conductive or resistive materials - H10P 30/204: {into Group IV semiconductors} - H10P 30/2042: {into crystalline silicon carbide} - H10P 30/21: {of electrically active species} - H10P 50/00: Etching of wafers, substrates or parts of devices - H10P 50/642: {Chemical etching} - H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) - H10D 8/01: Manufacture or treatment - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10D 62/117: {Shapes of semiconductor bodies} - H10D 64/64: Electrodes comprising a Schottky barrier to a semiconductor - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract It is the object of the invention to provide a power semiconductor rectifier with a low on-state-voltage and high blocking capability. The object is attained by a power semiconductor rectifier comprising: a drift layer having a first conductivity type; and an electrode layer forming a Schottky contact with the drift layer, wherein the drift layer includes a base layer having a peak net doping concentration, below 1·1016 cm−3 and a barrier modulation layer which is in direct contact with the electrode layer to form at least a part of the Schottky contact, wherein a net doping concentration of the barrier modulation layer is in a range between 1·1016cm−3 and 1·1019 cm−3 and wherein the barrier modulation layer has a layer thickness in a direction vertical to the interface between the electrode layer and the barrier modulation, layer of at least 1 nm and less than 0.2 μm. ## Claims ### Claim 1 Power semiconductor rectifier comprising: a drift layer having a first conductivity type; and an electrode layer forming a Schottky contact with the drift layer, wherein the drift layer includes a base layer having a peak net doping concentration below 1·1016 cm−3, wherein the drift layer includes a barrier modulation layer which is in direct contact with the electrode layer to form at least a part of the Schottky contact, wherein a net doping concentration of the barrier modulation layer is in a range between 1·1016 cm−3 and 1·1019 cm−3, the barrier modulation layer has a layer thickness in a direction vertical to the interface between the electrode layer and the barrier modulation layer of at least 1 nm and less than 0.2 μm. ### Claim 2 (depends on 1) Power semiconductor rectifier according to claim 1, wherein the base layer has a peak net doping concentration in a range between 8·1014 cm−3 and 6·1015 cm−3. ### Claim 3 (depends on 1) Power semiconductor rectifier according to claim 1, wherein the net doping concentration of the barrier modulation layer is in a range between 5·1016 cm−3 and 1·1019 cm−3. ### Claim 4 (depends on 3) Power semiconductor rectifier according to claim 3, wherein the net doping concentration of the barrier modulation layer is in a range between 1·1017 cm−3 and 5·1018 cm−3. ### Claim 5 (depends on 1) Power semiconductor rectifier according to claim 1, wherein the electrode layer penetrates through the barrier modulation layer to be in direct contact with the base layer, and wherein the contact between the electrode layer and the base layer is a first-barrier Schottky contact and the contact between the electrode layer and the barrier modulation layer is a second-barrier Schottky contact, the Schottky barrier height of the first-barrier Schottky contact being higher than that of the second-barrier Schottky contact. ### Claim 6 (depends on 5) Power semiconductor rectifier according to claim 5, wherein the drift layer has a first main side and a second main side parallel to the first main side, wherein the first-barrier Schottky contact includes a plurality of first-barrier Schottky contact sections, wherein the second-barrier Schottky contact includes a plurality of second-barrier Schottky contact sections, and wherein the first-barrier Schottky contact sections alternate with the second-barrier Schottky contact sections in at least one lateral direction parallel to the first main side. ### Claim 7 (depends on 6) Power semiconductor rectifier according to claim 6, wherein the first-barrier Schottky contact sections form a grid or honeycomb structure. ### Claim 8 (depends on 1) Power semiconductor rectifier according to claim 1, further comprising a plurality of emitter regions, wherein: each emitter region has a second conductivity type different from the first conductivity type, the electrode layer forms an ohmic contact with each one of the emitter regions, and each emitter region forms a pn-junction with the base layer. ### Claim 9 (depends on 1) Power semiconductor rectifier according to claim 1, wherein the drift layer is made of silicon carbide. ### Claim 10 Method for manufacturing a power semiconductor rectifier, the method comprising: forming a drift layer by forming a stack of a base layer and of a barrier modulation layer, wherein the base layer has a first conductivity type and has a peak net doping concentration below 1·10 16 cm−3, and wherein the barrier modulation layer has the first conductivity type, has a net doping concentration in a range between 1·1016 cm−3 and 1·1019 cm−3 and has layer thickness of at least 1 nm and less than 0.2 μm; and forming an electrode layer on the barrier modulation layer to form a Schottky contact with the barrier modulation layer. ### Claim 11 (depends on 10) Method for manufacturing a power semiconductor rectifier according to claim 10, the method further comprising, before the forming the electrode layer, forming at least one trench or hole into the drift layer, the trench or hole penetrating through the barrier modulation layer and extending into the base layer. ### Claim 12 (depends on 11) Method for manufacturing a power semiconductor rectifier according to claim 11, the method further comprising forming an emitter region at least at the bottom portion of the at least one trench or hole before the step of forming the electrode layer, wherein the emitter region has a second conductivity type different from the first conductivity type and forms a pn-junction with the drift layer, and wherein the electrode layer forms an ohmic contact with the emitter region. ### Claim 13 (depends on 12) Method for manufacturing a power semiconductor rectifier according to claim 12, wherein the emitter region is formed by depositing a semiconductor layer of the second conductivity type into the at least one trench or hole. ### Claim 14 (depends on 12) Method for manufacturing a power semiconductor rectifier according to claim 12, wherein the emitter region is formed by implanting a dopant of the second conductivity type into the drift layer at least at the bottom portion of the at least one trench or hole. ### Claim 15 (depends on 11) Method for manufacturing a power semiconductor rectifier according to claim 11, wherein the electrode layer is formed in the at least one trench or hole to form a Schottky contact with the base layer. ### Claim 16 (depends on 1) Power semiconductor rectifier according to claim 1, wherein the drift layer is made of silicon. ### Claim 17 (depends on 2) Power semiconductor rectifier according to claim 2, wherein the net doping concentration of the barrier modulation layer is in a range between 5·1016 cm−3 and 1·1019 cm−3. ### Claim 18 (depends on 2) Power semiconductor rectifier according to claim 2, wherein the electrode layer penetrates through the barrier modulation layer to be in direct contact with the base layer, and wherein the contact between the electrode layer and the base layer is a first-barrier Schottky contact and the contact between the electrode layer and the barrier modulation layer is a second-barrier Schottky contact, the Schottky barrier height of the first-barrier Schottky contact being higher than that of the second-barrier Schottky contact. ### Claim 19 (depends on 3) Power semiconductor rectifier according to claim 3, wherein the electrode layer penetrates through the barrier modulation layer to be in direct contact with the base layer, and wherein the contact between the electrode layer and the base layer is a first-barrier Schottky contact and the contact between the electrode layer and the barrier modulation layer is a second-barrier Schottky contact, the Schottky barrier height of the first-barrier Schottky contact being higher than that of the second-barrier Schottky contact. ### Claim 20 (depends on 2) Power semiconductor rectifier according to claim 2, further comprising a plurality of emitter regions, wherein: each emitter region has a second conductivity type different from the first conductivity type, the electrode layer forms an ohmic contact with each one of the emitter regions, and each emitter region forms a pn-junction with the base layer.