# US 10,121,907 B2 · Planar triple-implanted JFET

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- Number: US 10,121,907 B2
- Document ID: US10121907B2
- Status: Granted
- Kind: B2
- Application number: 15/267,177
- Filed: 2016-09-16
- Published: 2017-04-27
- Granted: 2018-11-06
- Earliest claimed: 2015-10-21
- Assignees: United Silicon Carbide, Inc.
- Applicants: United Silicon Carbide, Inc.
- Inventors: Anup Bhalla; Zhongda Li
- Web page: https://patentgrep.com/patent/US10121907B2

## CPC

- H10D 30/831: {Vertical FETs having PN junction gate electrodes (Vertical SIT H10D30/202)}
- H10D 12/031: {of IGBTs}
- H10D 30/0515: {of vertical FETs having PN homojunction gates}
- H10D 62/328: {having PN junction gates}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/8325: {Silicon carbide}
- H10D 64/411: {for FETs}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/22: using masks
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/149: {Source or drain regions of field-effect devices}
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS

## Abstract

A JFET is formed with vertical and horizontal elements made from a high band-gap semiconductor material such as silicon carbide via triple implantation of a substrate comprising an upper drift region and a lower drain region, the triple implantation forming a lower gate, a horizontal channel, and an upper gate, in a portion of the drift region. A source region may be formed through a portion of the top gate, and the top and bottom gates are connected. A vertical channel region is formed adjacent to the planar JFET region and extending through the top gate, horizontal channel, and bottom gate to connect to the drift, such that the lower gate modulates the vertical channel as well as the horizontal channel, and current from the sources flows first through the horizontal channel and then through the vertical channel into the drift.

## Claims

### Claim 1

A method for creating a junction field-effect transistor (JFET), comprising:
a. applying a first mask to a wafer to form a first patterned hard masking layer to the top of the wafer, the wafer comprising an upper drift region and a bottom drain region;
b. with the first mask in place, applying three implants to a first unmasked portion of the top of the wafer to form a first lower gate, a first horizontal channel, and a first top gate in an upper portion of the drift region;
c. forming a first source in a portion of the first top gate;
d. connecting the first top gate to the first lower gate; and
e. forming a vertical channel via implantation, the vertical channel being at a distance from the first source, such that the vertical channel abuts the first top gate, the first horizontal channel, the first lower gate, and the drift region.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
f. forming the vertical channel via angled implantation with the first patterned hard masking layer in place.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
f. with the first mask in place, applying the three implants to a second unmasked portion of the top of the wafer to form a second lower gate, a second horizontal channel, and a second top gate in an upper portion of the drift region,
g. wherein, the vertical channel further abuts the second top gate, the second horizontal channel, and the second lower gate;
h. forming a second source in a portion of the second top gate, the second source being at a distance from the second source; and
i. connecting the second top gate and the second lower gate to the first top gate and the first lower gate.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
j. forming the vertical channel via angled implantation with the first patterned hard masking layer in place.

### Claim 5 (depends on 3)

The method of claim 3, further comprising:
j. forming a lightly doped regions surrounding the first source and the second source via implantation, where the lightly doped regions are doped at ten percent or less of the level of doping of the first source and the second source.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
e. forming a lightly doped region surrounding the first source via implantation, where the lightly doped region is doped at ten percent or less of the level of doping of the first source.

### Claim 7

A method for creating a junction field-effect transistor (JFET), comprising:
a. applying a first mask to a wafer to form a first patterned hard masking layer to the top of the wafer, the wafer comprising an upper drift region and a bottom drain region;
b. applying three implants to an unmasked portion of the top of the wafer to form a lower gate region, a horizontal channel region, and a top gate region in an upper portion of the drift region;
c. forming a source region in a portion of the top gate region;
d. connecting the top and lower gate regions;
e. forming a vertical channel region via implantation, the vertical channel region being at a distance from the source region, the vertical channel region being adjacent to, and extending through, the top gate region, the horizontal channel region, and the lower gate region, to connect to the drift region; and
f. forming a lightly doped region surrounding the source region via implantation, where the lightly doped region is doped at ten percent or less of the level of doping of the source region.

### Claim 8

A method for creating a junction field-effect transistor (JFET), comprising:
a. applying a first mask to a wafer to form a first patterned hard masking layer to the top of the wafer, the wafer comprising an upper drift region and a bottom drain region;
b. applying three implants to an unmasked portion of the top of the wafer to form a lower gate region, a horizontal channel region, and a top gate region in an upper portion of the drift region;
c. forming a source region in a portion of the top gate region;
d. connecting the top and lower gate regions; and
e. forming two vertical channels via implantation, one at each end of a region comprising the upper gate, the lower gate, and the horizontal channel,
f. wherein the vertical channels are at a distance from the source, and wherein the vertical channels abut the top gate, the horizontal channel, and the lower gate, and the drift region.