# US 10,121,906 B2 · Vertical memory strings, and vertically-stacked structures

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- Number: US 10,121,906 B2
- Document ID: US10121906B2
- Status: Granted
- Kind: B2
- Application number: 15/467,765
- Filed: 2017-03-23
- Published: 2017-07-06
- Granted: 2018-11-06
- Earliest claimed: 2013-01-07
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: John D. Hopkins
- Web page: https://patentgrep.com/patent/US10121906B2

## CPC

- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/689: {Vertical floating-gate IGFETs}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/681: {having a compositional variation, e.g. multilayered}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.

## Claims

### Claim 1

A vertically-stacked structure, comprising:
an etchstop material over a base, the etchstop material comprising tungsten silicide;
a stack of alternating electrically conductive levels and electrically insulative levels over the etchstop material;
electrically insulative pillars that extends through the stack and contact an upper surface of the etch stop material;
channel material posts between the pillars, the channel material posts extending through the etchstop material and having a first pair of opposing sides and a second pair of opposing sides; the first pair of opposing sides being spaced from adjacent pillars by intervening regions of the stack; none of the stack being present between each of the sides of the second pair of opposing sides and pillars adjacent such sides of the second pair;
gate dielectric material along exposed edges of the electrically conductive levels and the channel material posts; and
memory cells within the conductive levels and separated from the channel material posts by the gate dielectric.

### Claim 2 (depends on 1)

The structure of claim 1 wherein the memory cells comprise a charge storage material, a control gate material and a charge blocking material.

### Claim 3 (depends on 2)

The structure of claim 2 wherein charge blocking material is disposed between and contacts the control gate material and the charge storage material.

### Claim 4 (depends on 2)

The structure of claim 2 wherein the charge storage material is in contact with the gate dielectric material.

### Claim 5 (depends on 2)

The structure of claim 2 wherein each of the charge storage material, the charge blocking material and the control gate material is in contact with electrically insulative material comprised by the electrically insulative levels.

### Claim 6 (depends on 2)

The structure of claim 2 wherein the charge blocking material comprises silicon nitride between two silicon oxide structures.

### Claim 7 (depends on 6)

The vertical memory string of claim 6 wherein the electrically conductive levels have a thickness along a cross-section, and wherein the charge-storage material within each the electrically conductive levels has a same thickness along the cross-section as the electrically conductive levels.

### Claim 8

A vertical memory string, comprising:
a stack of alternating electrically conductive levels and electrically insulative levels over a base, the stack having an elevationally lowest surface on an upper surface of the base;
a trench extending through the stack to the upper surface of the base;
cavities extending from the trench into the conductive levels;
electrically insulative pillars consisting essentially of silicon dioxide extending within the trench through the stack and having bottom surfaces on the upper surface of the base;
channel material posts within the trench extending through the stack, the channel material posts extending elevationally lower that the bottom surface of the electrically insulative pillars and being in direct contact with the electrically insulative pillars;
charge blocking material within the cavities along exposed edges of the electrically conductive levels;
memory cell material within the cavities; and
a gate dielectric material between the memory cell material and the channel material posts.

### Claim 9 (depends on 8)

The vertical memory string of claim 8 wherein the memory cell material comprises a charge storage material and a charge blocking material.

### Claim 10 (depends on 9)

The vertical memory string of claim 9 wherein the charge storage material contacts the gate dielectric material.

### Claim 11 (depends on 9)

The vertical memory string of claim 9 wherein the memory cell material further comprises a control gate material.

### Claim 12 (depends on 11)

The vertical memory string of claim 11 wherein the charge blocking material is disposed laterally between and contacting the charge storage material and the control gate material.

### Claim 13 (depends on 11)

The vertical memory string of claim 11 wherein the charge blocking material comprises a silicon nitride structure laterally between silicon dioxide structures.

### Claim 14

A semiconductor construction, comprising:
an etchstop material over a semiconductor base;
a stack of alternating electrically conductive levels and electrically insulative levels over the etchstop material;
electrically insulative pillars extending through the stack and contacting an upper surface of the etchstop material;
channel material posts between the pillars; the channel material posts extending through the etchstop material and having a first pair of opposing sides and a second pair of opposing sides; the first pair of opposing sides being spaced from adjacent pillars by intervening regions of the stack; none of the stack being present between each of the sides of the second pair of opposing sides and pillars adjacent such sides of the second pair;
memory cells disposed within the conductive levels, the memory cells comprising:
a control gate material;
a charge-storage material and
a charge blocking material disposed between and contacting the control gate material and the charge-storage material; and
gate dielectric material between the charge-storage material and the channel material posts.

### Claim 15 (depends on 14)

The construction of claim 14 wherein the charge-storage material comprises floating gate material.

### Claim 16 (depends on 14)

The construction of claim 14 wherein the charge-storage material comprises charge-trapping material.

### Claim 17 (depends on 14)

The construction of claim 14 wherein the charge blocking material comprises silicon dioxide.

### Claim 18 (depends on 14)

The construction of claim 14 wherein the charge blocking material comprises a silicon nitride structure sandwiched between a pair of silicon dioxide structures.

### Claim 19 (depends on 14)

The construction of claim 14 wherein the electrically conductive levels comprise conductively doped silicon, and wherein the electrically insulative levels comprise silicon dioxide.

### Claim 20 (depends on 14)

The construction of claim 14 wherein the posts and pillars are part of a serpentining structure that extends through the stack; the serpentining structure separating the control gates into a first set on one side of the serpentining structure and a second set on an opposing side of the serpentining structure; all control gates of the first set that are at a common vertical level are electrically coupled to one another, and all control gates of the second set that are at a common vertical level are electrically coupled to one another but not to the control gates of the first set.

### Claim 21 (depends on 14)

The construction of claim 14 wherein the channel material posts are entirely laterally surrounded by the gate dielectric material.

### Claim 22 (depends on 14)

The construction of claim 14 wherein the channel material posts are spaced from the electrically insulative pillars by only the gate dielectric material along a cross-section.