# US 10,121,902 B2 · Semiconductor integrated circuit device including nano-wire selector and method of manufacturing the same

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- Number: US 10,121,902 B2
- Document ID: US10121902B2
- Status: Granted
- Kind: B2
- Application number: 15/371,358
- Filed: 2016-12-07
- Published: 2018-03-01
- Granted: 2018-11-06
- Earliest claimed: 2016-08-26
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Dong Yean Oh
- Web page: https://patentgrep.com/patent/US10121902B2

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/299: {having lateral doping variations (IGFETs having lightly doped source or drain extensions H10D30/601)}
- H10D 62/834: further characterised by the dopants
- H10D 64/01: Manufacture or treatment
- H10D 64/01322: {the conductor contacting the insulator having a lateral variation in doping, composition or deposition steps}
- H10D 64/511: {for IGFETs}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 34/42: with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20)
- H10P 95/94: {Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In a method of manufacturing a semiconductor integrated circuit device, an active region including a nano-wire may be formed on a bulk insulating layer. A hard mask pattern may be formed to partially expose the nano-wire. A work function-controlling region may be formed on the nano-wire exposed through the hard mask pattern. The hard mask pattern may be removed. A gate insulating layer may be formed on the nano-wire. A gate may be formed to surround the nano-wire.

## Claims

### Claim 1

A method of manufacturing a semiconductor integrated circuit device, the method comprising:
forming an active region including a nano-wire on a bulk insulating layer;
forming a hard mask pattern configured to partially expose the nano-wire;
forming a work function-controlling region on the nano-wire exposed through the hard mask pattern;
removing the hard mask pattern;
forming a gate insulating layer on the nano-wire;
forming a gate configured to surround the nano-wire; and
forming a source and a drain in the active region at both sides of the gate,
wherein the hard mask pattern is formed on the bulk insulating layer to expose at least one region of the nano-wire corresponding to an edge of the gate, and
wherein the work function-controlling region is formed to include a depth less than a radius of the nano-wire.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the active region including the nano-wire comprises:
forming a semiconductor layer on the bulk insulating layer;
patterning the semiconductor layer to define pad regions and a nano-wire region, the nano-wire region extended from the pad regions and the nano-wire region having a width narrower than that of each of the pad regions;
etching the bulk insulating layer corresponding to the nano-wire region to form a groove under the nano-wire; and
slimming the semiconductor layer corresponding to the nano-wire region to form the nano-wire.

### Claim 3 (depends on 2)

The method of claim 2, wherein etching the bulk insulating layer corresponding to the nano-wire region comprises isotropically etching the bulk insulating layer at a peripheral portion of the nano-wire region.

### Claim 4 (depends on 2)

The method of claim 2, wherein slimming the semiconductor layer comprises annealing using hydrogen an upper surface of the nano-wire region and a surface of the nano-wire region exposed through the groove.

### Claim 5 (depends on 1)

The method of claim 1, wherein the hard mask pattern is formed on the bulk insulating layer to expose a portion of the nano-wire overlapped with the gate and edges of the gate.

### Claim 6 (depends on 1)

The method of claim 1, wherein the hard mask pattern is formed on the bulk insulating layer to expose a region positioned adjacent to the drain.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the work function-controlling region comprises doping the nano-wire with a semiconductor material having a band gap different from a band gap of the nano-wire.

### Claim 8 (depends on 7)

The method of claim 7, wherein when the nano-wire comprises an N type silicon, and
wherein the work function-controlling region comprises any one selected from the group consisting of SiGe, GaAs, InAs, GaSb, InSb, InP, MgS, MgSe, MaTe, ZnS, ZnSe, ZnTe, AlP, GaP, AlAs, AlSb, CdS, CdSe and CdTe.

### Claim 9 (depends on 7)

The method of claim 7, wherein when the nano wire comprises a P type silicon, the work function-controlling region comprises any one selected from the group consisting of SiC, AlN, GaN, ZnS, ZnO, ZnSe, CdS, BP, InN and CdSe.

### Claim 10 (depends on 7)

The method of claim 7, wherein the work function-controlling region is doped with the semiconductor material by a pulsed laser ablation deposition (PLAD) process.

### Claim 11 (depends on 1)

The method of claim 1, wherein forming the gate comprises:
forming a conductive layer having a first work function on the bulk insulating layer with the nano-wire; and
anisotropically etching the conductive layer having the first work function to surround a channel region of the nano-wire.

### Claim 12 (depends on 1)

The method of claim 1, wherein forming the gate comprises:
forming a first conductive layer having a first work function on the bulk insulating layer with the nano-wire;
anisotropically etching the first conductive layer having the first work function to form a first gate configured to surround a channel region of the nano-wire;
forming a second conductive layer having a second work function on a surface of the nano-wire with the first gate; and
anisotropically etching the second conductive layer having the second work function to form a second gate at both sides of the first gate,
wherein the second work function is lower than the first work function.

### Claim 13 (depends on 1)

The method of claim 1, further comprising:
forming an insulating interlayer on the active region;
etching the insulating interlayer to form a contact hole configured to expose the source and the drain; and
forming a first contact plug contacted with the source and a second contact plug contacted with the drain.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
recessing the second contact plug by a predetermined depth, to form a heating electrode; and
forming a storage layer on the heating electrode.