# US 10,121,897 B2 · Field effect transistor with narrow bandgap source and drain regions and method of fabrication

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- Number: US 10,121,897 B2
- Document ID: US10121897B2
- Status: Granted
- Kind: B2
- Application number: 15/660,574
- Filed: 2017-07-26
- Published: 2017-11-09
- Granted: 2018-11-06
- Earliest claimed: 2005-02-23
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Robert S. Chau; Suman Datta; Jack Kavalieros; Justin K. Brask; Mark L. Doczy; Matthew Metz
- Web page: https://patentgrep.com/patent/US10121897B2

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/605: {having significant overlap between the lightly-doped extensions and the gate electrode}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/82: Heterojunctions
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 62/852: being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP
- H10D 62/854: further characterised by the dopants
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

## Claims

### Claim 1

A transistor comprising:
a gate dielectric layer formed over a substrate;
a gate electrode formed on the gate dielectric layer; and
a pair of source/drain regions on opposite sides of the gate electrode, the pair of source/drain regions comprising a doped semiconductor film comprising a material selected from the group consisting of InSb, InAs, InP and InGaAs; and wherein the semiconductor film is doped to a p type conductivity with a carbon (C), a cadmium (Cd), a zinc (Zn), or a chromium (Cr) dopant.

### Claim 2 (depends on 1)

The transistor of claim 1, wherein the semiconductor film comprises InAs.

### Claim 3 (depends on 1)

The transistor of claim 1, further comprising a pair of non-alloyed ohmic contacts directly on the semiconductor film on opposite sides of the gate electrode.

### Claim 4 (depends on 3)

The transistor of claim 3, wherein at least one of the non-alloyed ohmic contacts comprises a gold layer on a titanium layer.

### Claim 5 (depends on 1)

The transistor of claim 1, wherein the doped semiconductor film extends beneath at least a portion of the gate electrode.

### Claim 6 (depends on 1)

The transistor of claim 1, wherein the semiconductor film is formed in a pair of recesses in the substrate on opposite sides of the gate electrode.

### Claim 7 (depends on 1)

The transistor of claim 1, wherein the substrate comprises a buried oxide layer.

### Claim 8 (depends on 7)

The transistor of claim 7, wherein the buried oxide layer has a thickness between 200-2,000 angstroms.

### Claim 9 (depends on 1)

The transistor of claim 1, wherein the semiconductor film is doped with a concentration level between 1×1016-1×1019 atoms/cm3 of the Si dopant.

### Claim 10 (depends on 1)

The transistor of claim 1, wherein the gate dielectric layer comprises at least one of tantalum pentaoxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, lead zirconium titanate (PZT), or barium strontium titanate (BST).

### Claim 11

A transistor comprising:
a substrate comprising a body having a top surface opposite a bottom surface and a pair of sidewalls;
a gate dielectric layer on the body along the top surface and the pair of sidewalls of the body;
a gate electrode on the gate dielectric layer along the top surface and the pair of sidewalls of the body; and
a pair of non-planar source/drain regions on the body on opposite sides of the gate electrode, the pair of non-planar source/drain regions comprising an in situ doped semiconductor film comprising a material selected from the group consisting of InSb, InAs, InP and InGaAs, wherein the semiconductor film is doped to a p type conductivity with a carbon (C), a cadmium (Cd), a zinc (Zn), or a chromium (Cr) dopant.

### Claim 12 (depends on 11)

The transistor of claim 11, wherein the semiconductor film comprises InAs.

### Claim 13 (depends on 11)

The transistor of claim 11, further comprising a pair of non-alloyed metal contacts directly on the semiconductor film on opposite sides of the gate electrode.

### Claim 14 (depends on 11)

The transistor of claim 11, wherein the semiconductor film extends above the top surface.

### Claim 15 (depends on 11)

The transistor of claim 11, wherein the substrate comprises a buried oxide layer.

### Claim 16 (depends on 11)

The transistor of claim 11, wherein the semiconductor film is formed in a pair of recesses in the body on opposite sides of the gate electrode.

### Claim 17 (depends on 15)

The transistor of claim 15, wherein the body is on the buried oxide layer.

### Claim 18 (depends on 15)

The transistor of claim 15, wherein the buried oxide layer has a thickness between 200-2,000 angstroms.

### Claim 19 (depends on 11)

The transistor of claim 11, wherein the semiconductor film is doped with a concentration level between 1×1016-1×1019 atoms/cm3 of the Si dopant.

### Claim 20 (depends on 11)

The transistor of claim 11, wherein the gate dielectric layer comprises at least one of tantalum pentaoxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, lead zirconium titanate (PZT), or barium strontium titanate (BST).