# US 10,121,895 B2 · Method for producing semiconductor device and semiconductor device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,121,895 B2
- Document ID: US10121895B2
- Status: Granted
- Kind: B2
- Application number: 15/952,956
- Filed: 2018-04-13
- Published: 2018-08-16
- Granted: 2018-11-06
- Earliest claimed: 2018-04-13
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Tadashi Yamaguchi
- Web page: https://patentgrep.com/patent/US10121895B2

## CPC

- H10D 30/794: {comprising conductive materials, e.g. silicided source, drain or gate electrodes}
- H10B 43/30: characterised by the memory core region
- H10B 43/40: characterised by the peripheral circuit region
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 1/00: Resistors, capacitors or inductors
- H10D 30/0212: {using self-aligned silicidation}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P 14/418: {the conductive layers comprising transition metals}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device having a memory cell includes: a first gate electrode formed on a semiconductor substrate via a first insulating film; a second gate electrode formed on the semiconductor substrate via the second insulating film having a charge storage portion inside so as to be adjacent to the first gate electrode; a third insulating film interposed between the first gate electrode and the second gate electrode; a first source/drain region formed on a main surface of the semiconductor substrate; a first silicide layer formed in contact with an upper surface of the first source/drain region; a second silicide layer formed in contact with an upper surface of the first gate electrode; and a third silicide layer formed in contact with an upper surface of the second gate electrode. The first to third silicide layers contain platinum.

## Claims

### Claim 1

A semiconductor device having a memory cell comprising:
a semiconductor substrate;
a first gate electrode formed on the semiconductor substrate via a first insulating film;
a second gate electrode formed on the semiconductor substrate via the second insulating film having a charge storage portion inside so as to be adjacent to the first gate electrode;
a third insulating film interposed between the first gate electrode and the second gate electrode;
a first source/drain region formed on a main surface of the semiconductor substrate;
a first silicide layer formed in contact with an upper surface of the first source/drain region;
a second silicide layer formed in contact with an upper surface of the first gate electrode; and
a third silicide layer formed in contact with an upper surface of the second gate electrode,
wherein the first to third silicide layers contain platinum, and
an amount of platinum per unit area of a lower surface of the first silicide layer is larger than an amount of platinum per unit area of a lower surface of each of the second silicide layer and the third silicide layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein a tensile stress of the first silicide layer is larger than a tensile stress of each of the second silicide layer and the third silicide layer.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1,
wherein the first to third silicide layers have a polycrystalline structure, and
a number of (010) oriented grains per unit volume in the first silicide layer is larger than a number of (010) oriented grains per unit volume in each of the second silicide layer and the third silicide layer.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
wherein the first to third silicide layers contain platinum, and
an amount of platinum per unit area of an upper surface of the first silicide layer is smaller than an amount of platinum per unit area of an upper surface of each of the second silicide layer and the third silicide layer.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, further comprising a field effect transistor including:
a metal gate electrode formed on the semiconductor substrate via a fourth insulating film;
a second source/drain region formed on a main surface of the semiconductor substrate; and
a fourth silicide layer formed in contact with an upper surface of the second source/drain region,
wherein the first to fourth silicide layers contain platinum, and
an amount of platinum per unit area of a lower surface of the fourth silicide layer is larger than an amount of platinum per unit area of a lower surface of each of the second silicide layer and the third silicide layer.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5,
wherein a tensile stress of the fourth silicide layer is larger than a tensile stress of each of the second silicide layer and the third silicide layer.

### Claim 7 (depends on 5)

The semiconductor device according to claim 5,
wherein the first to fourth silicide layers have a polycrystalline structure, and
a number of (010) oriented grains per unit volume in the fourth silicide layer is larger than a number of (010) oriented grains per unit volume in each of the second silicide layer and the third silicide layer.

### Claim 8 (depends on 5)

The semiconductor device according to claim 5,
wherein the first to fourth silicide layers contain platinum, and
an amount of platinum per unit area of an upper surface of the fourth silicide layer is smaller than an amount of platinum per unit area of an upper surface of each of the second silicide layer and the third silicide layer.