# US 10,121,893 B2 · Integrated circuit structure without gate contact and method of forming same

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- Number: US 10,121,893 B2
- Document ID: US10121893B2
- Status: Granted
- Kind: B2
- Application number: 15/797,634
- Filed: 2017-10-30
- Published: 2018-03-01
- Granted: 2018-11-06
- Earliest claimed: 2016-08-26
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Hui Zang; Manfred J Eller; Min-Hwa Chi; Jerome J. B. Ciavatti
- Web page: https://patentgrep.com/patent/US10121893B2

## CPC

- H10D 30/721: {having a gate-to-body connection, i.e. bulk dynamic threshold voltage IGFET (TFTs having gate-to-body connection H10D30/6708)}
- H10B 10/12: {comprising a MOSFET load element}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 64/668: {the layer being a silicide, e.g. TiSi2}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a channel region within the fin; and a source/drain contact extending within the dielectric layer to a source/drain region within a fin, the source/drain contact being separated from the gate structure by at least one gate spacer in the pair of gate spacers, wherein the channel region and the source/drain region provide electrical connection between the gate structure and the source/drain contact.

## Claims

### Claim 1

An integrated circuit structure comprising:
a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a doped channel region within the fin; and
a source/drain contact extending within the dielectric layer to a source/drain region within the fin, the source/drain contact being separated from the gate structure by at least one gate spacer of the pair of gate spacers,
wherein the doped channel region and the source/drain region provide electrical connection between the gate structure and the source/drain contact.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the doped channel region within the fin includes at least one n-type or p-type dopant.

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, wherein the at least a portion of the gate structure is disposed over a portion of a shallow trench isolation (STI) region.

### Claim 4 (depends on 1)

The integrated circuit structure of claim 1, wherein the integrated circuit structure is free from a gate contact directly to the gate structure.

### Claim 5 (depends on 1)

The integrated circuit structure of claim 1, where the gate structure directly contacts the doped channel region.

### Claim 6

An integrated circuit structure comprising:
a source/drain contact to a source/drain region, the source/drain contact being adjacent to a gate structure and being directly connected to a gate conductor of the gate structure by direct contact with a sidewall of the gate conductor.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, wherein the source/drain contact is connected to the gate conductor through opposing sidewalls of the gate structure.

### Claim 8 (depends on 6)

The integrated circuit structure of claim 6, wherein at least a portion of the gate structure is disposed over a portion of a shallow trench isolation (STI) region.

### Claim 9 (depends on 6)

The integrated circuit structure of claim 6, further comprising:
a gate cap layer over the gate structure,
wherein the source/drain contact is directly connected to the gate conductor beneath the gate cap layer.

### Claim 10

An integrated circuit structure comprising:
a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a doped channel region within the fin, the doped channel region including a silicide region therein; and
a source/drain contact extending within the dielectric layer to a source/drain region within the fin, the source/drain contact being separated from the gate structure by at least one gate spacer of the pair of gate spacers,
wherein the doped channel region including the silicide region and the source/drain region provide electrical connection between the gate structure and the source/drain contact.

### Claim 11 (depends on 10)

The integrated circuit structure of claim 10, wherein the gate structure further includes a conductor over the silicide region.

### Claim 12 (depends on 10)

The integrated circuit structure of claim 10, wherein the at least a portion of the gate structure is disposed over a portion of a shallow trench isolation (STI) region.

### Claim 13 (depends on 10)

The integrated circuit structure of claim 10, wherein the integrated circuit structure is free from a gate contact directly to the gate structure.

### Claim 14 (depends on 10)

The integrated circuit structure of claim 10, wherein the gate structure directly contacts the silicide region.