# US 10,121,891 B2 · P-N bimodal transistors

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- Number: US 10,121,891 B2
- Document ID: US10121891B2
- Status: Granted
- Kind: B2
- Application number: 15/364,971
- Filed: 2016-11-30
- Published: 2017-03-23
- Granted: 2018-11-06
- Earliest claimed: 2015-09-22
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Yongxi Zhang; Sameer P. Pendharkar; Henry Litzmann Edwards
- Web page: https://patentgrep.com/patent/US10121891B2

## CPC

- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 84/151: {LDMOS having built-in components}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/657: {having substrates comprising insulating layers, e.g. SOI-LDMOS transistors}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.

## Claims

### Claim 1

A transistor, comprising:
a doped layer having a first conductivity type;
a buried layer in the doped layer, the buried layer having a second conductivity type opposite the first conductivity type;
a first terminal region having a first n-doped region and a first p-doped region adjacent to the first n-doped region;
a second terminal region having a second n-doped region and a second p-doped region adjacent to the second n-doped region;
a surface doped region having the second conductivity type and positioned between the first and second terminal regions;
a first gate positioned above and between the first p-doped region and the surface doped region; and
a second gate positioned above and between the surface doped region and the second n-doped region.

### Claim 2 (depends on 1)

The transistor of claim 1, wherein:
the first p-doped region positioned laterally between the first n-doped region and the surface doped region; and
the second n-doped region positioned laterally between the surface doped region and the second p-doped region.

### Claim 3 (depends on 1)

The transistor of claim 1, wherein the first gate is associated with a p-channel between the first p-doped region and the second p-doped region.

### Claim 4 (depends on 1)

The transistor of claim 1, wherein the second gate is associated with an n-channel between the first n-doped region and the second n-doped region.

### Claim 5 (depends on 1)

The transistor of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

### Claim 6 (depends on 5)

The transistor of claim 5, further comprising:
a third p-doped region inside the surface doped region and having a higher doping concentration than the surface doped region, the third p-doped region coupled to the second p-doped region,
wherein the second gate is positioned above and between the third p-doped region and the second n-doped region.

### Claim 7 (depends on 5)

The transistor of claim 5, further comprising:
a p-doped well region surrounding the second terminal region.

### Claim 8 (depends on 5)

The transistor of claim 5, further comprising:
n-doped well region surrounding the first terminal region.

### Claim 9 (depends on 1)

The transistor of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.

### Claim 10 (depends on 9)

The transistor of claim 9, further comprising:
a third n-doped region inside the surface doped region and having a higher doping concentration than the surface doped region, the third n-doped region coupled to the first n-doped region,
wherein the first gate is positioned above and between the first p-doped region and the third n-doped region.

### Claim 11 (depends on 1)

The transistor of claim 1, wherein the first n-doped region abuts the first p-doped region.

### Claim 12 (depends on 1)

The transistor of claim 1, wherein the second n-doped region abuts the second p-doped region.

### Claim 13 (depends on 1)

The transistor of claim 1, wherein the first n-doped region abuts the first p-doped region and the second n-doped region abuts the second p-doped region.

### Claim 14

A transistor, comprising:
n-doped layer;
a p-doped buried layer in the n-doped layer;
a first terminal region having a first n-doped region and a first p-doped region adjacent to the first n-doped region;
a second terminal region having a second n-doped region and a second p-doped region adjacent to the second n-doped region;
a p-doped surface region positioned between the first and second terminal regions;
a first gate positioned above and between the first p-doped region and the p-doped surface region; and
a second gate positioned above and between the p-doped surface region and the second n-doped region.

### Claim 15 (depends on 14)

The transistor of claim 14, wherein:
the first p-doped region positioned laterally between the first n-doped region and the p-doped surface region; and
the second n-doped region positioned laterally between the p-doped surface region and the second p-doped region.

### Claim 16 (depends on 14)

The transistor of claim 14, wherein:
the first gate is associated with a p-channel between the first p-doped region and the second p-doped region; and
the second gate is associated with an n-channel between the first n-doped region and the second n-doped region.

### Claim 17 (depends on 14)

The transistor of claim 14, further comprising:
a third p-doped region inside the p-doped surface region and having a higher doping concentration than the p-doped surface region, the third p-doped region coupled to the second p-doped region,
wherein the second gate is positioned above and between the third p-doped region and the second n-doped region.

### Claim 18 (depends on 14)

The transistor of claim 14, further comprising:
a p-doped well region surrounding the second terminal region,
wherein the p-doped buried layer is connected to the p-doped surface region and the p-doped well region.

### Claim 19 (depends on 14)

The transistor of claim 14, further comprising:
an n-doped well region surrounding the first terminal region.

### Claim 20 (depends on 14)

The transistor of claim 14, wherein the first n-doped region abuts the first p-doped region.

### Claim 21 (depends on 14)

The transistor of claim 14, wherein the second n-doped region abuts the second p-doped region.

### Claim 22 (depends on 14)

The transistor of claim 14, wherein the first n-doped region abuts the first p-doped region and the second n-doped region abuts the second p-doped region.

### Claim 23

A transistor, comprising:
a p-doped layer;
n-doped buried layer in the p-doped layer;
a first terminal region having a first n-doped region and a first p-doped region adjacent to the first n-doped region;
a second terminal region having a second n-doped region and a second p-doped region adjacent to the second n-doped region;
an n-doped surface region positioned between the first and second terminal regions;
a first gate positioned above and between the first p-doped region and the n-doped surface region; and
a second gate positioned above and between the n-doped surface region and the second n-doped region.

### Claim 24 (depends on 23)

The transistor of claim 23, wherein:
the first p-doped region positioned laterally between the first n-doped region and the n-doped surface region; and
the second n-doped region positioned laterally between the n-doped surface region and the second p-doped region.

### Claim 25 (depends on 24)

The transistor of claim 24, wherein the first n-doped region abuts the first p-doped region.

### Claim 26 (depends on 24)

The transistor of claim 24, wherein the second n-doped region abuts the second p-doped region.

### Claim 27 (depends on 24)

The transistor of claim 24, wherein the first n-doped region abuts the first p-doped region and the second n-doped region abuts the second p-doped region.

### Claim 28 (depends on 23)

The transistor of claim 23, wherein:
the first gate is associated with a p-channel between the first p-doped region and the second p-doped region; and
the second gate is associated with an n-channel between the first n-doped region and the second n-doped region.

### Claim 29 (depends on 23)

The transistor of claim 23, further comprising:
a third n-doped region inside the n-doped surface region and having a higher doping concentration than the n-doped surface region, the third n-doped region coupled to the first n-doped region,
wherein the first gate is positioned above and between the first p-doped region and the third n-doped region.

### Claim 30

A method of making a transistor, comprising:
providing a doped layer having a first conductivity type;
providing a buried layer in the doped layer, the buried layer having a second conductivity type opposite the first conductivity type;
providing a first terminal region having a first n-doped region and a first p-doped region adjacent to the first n-doped region;
providing a second terminal region having a second n-doped region and a second p-doped region adjacent to the second n-doped region;
providing a surface doped region having the second conductivity type and positioned between the first and second terminal regions;
providing a first gate positioned above and between the first p-doped region and the surface doped region; and
providing a second gate positioned above and between the surface doped region and the second n-doped region.

### Claim 31

A method of making a transistor, comprising:
providing an n-doped layer;
providing a p-doped buried layer in the n-doped layer;
providing a first terminal region having a first n-doped region and a first p-doped region adjacent to the first n-doped region;
providing a second terminal region having a second n-doped region and a second p-doped region adjacent to the second n-doped region;
providing a p-doped surface region positioned between the first and second terminal regions;
providing a first gate positioned above and between the first p-doped region and the p-doped surface region; and
providing a second gate positioned above and between the p-doped surface region and the second n-doped region.

### Claim 32

A method of making a transistor, comprising:
providing a p-doped layer;
providing an n-doped buried layer in the p-doped layer;
providing a first terminal region having a first n-doped region and a first p-doped region adjacent to the first n-doped region;
providing a second terminal region having a second n-doped region and a second p-doped region adjacent to the second n-doped region;
providing an n-doped surface region positioned between the first and second terminal regions;
providing a first gate positioned above and between the first p-doped region and the n-doped surface region; and
providing a second gate positioned above and between the n-doped surface region and the second n-doped region.