# US 10,121,890 B2 · High voltage transistor structure

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- Number: US 10,121,890 B2
- Document ID: US10121890B2
- Status: Granted
- Kind: B2
- Application number: 15/018,605
- Filed: 2016-02-08
- Published: 2016-06-02
- Granted: 2018-11-06
- Earliest claimed: 2011-12-23
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ker Hsiao Huo; Chih-Chang Cheng; Ru-Yi Su; Jen-Hao Yeh; Fu-Chih Yang; Chun Lin Tsai
- Web page: https://patentgrep.com/patent/US10121890B2

## CPC

- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 12/01: Manufacture or treatment
- H10D 12/031: {of IGBTs}
- H10D 12/411: {Insulated-gate bipolar transistors [IGBT]}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 62/114: {PN junction isolations}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10P 30/20: into semiconductor materials, e.g. for doping
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An embodiment of a structure provides an enhanced performing high voltage device, configured as a lateral diffused MOS (HV LDMOS) formed in a tri-well structure (a small n-well in an extended p-type well inside an n-type well) within the substrate with an anti-punch through layer and a buried layer below the n-type well, which reduces substrate leakage current to almost zero. The drain region is separated into two regions, one within the small n-well and one contacting the outer n-type well such that the substrate is available for electric potential lines during when a high drain voltage is applied.

## Claims

### Claim 1

A high voltage semiconductor transistor, comprising:
a semiconductor substrate having a first type of conductivity; a first well region having a second type of conductivity and formed over the semiconductor substrate;
a second well region in the first well region and having the first type of conductivity; a first insulating structure over the first well region;
a gate structure adjacent the first insulating structure and between a source region and a drain region;
the drain region comprising a first drain portion between the first insulating structure and a second insulating structure and a second drain portion across the second insulating structure from the first drain portion, wherein the first drain portion has the first type of conductivity and the second drain portion has the second type of conductivity; and
wherein the first type of conductivity is different from the second type of conductivity; and
the source region disposed on a side of the gate structure opposite from the drain region.

### Claim 2 (depends on 1)

The transistor of claim 1, wherein the second well region has a U-shape in a cross section and extends from an interface with the source region to an interface with the second insulating structure, and the cross section is taken in a direction perpendicular to a top surface of the semiconductor substrate.

### Claim 3 (depends on 1)

The transistor of claim 1, wherein the gate structure includes a gate dielectric layer and a gate electrode layer, wherein the gate electrode layer is disposed on a surface of the first insulating structure.

### Claim 4 (depends on 1)

The transistor of claim 1, wherein the first type of conductivity is p-type and the second type of conductivity is n-type.

### Claim 5 (depends on 1)

The transistor of claim 1, wherein the source region has a first source portion and a second source portion, the second source portion abutting the first source portion.

### Claim 6 (depends on 5)

The transistor of claim 5, wherein the first source portion has the first type of conductivity and the second source portion has the second type of conductivity, and wherein the first drain portion has the first type of conductivity and the second second type of conductivity.

### Claim 7 (depends on 1)

The transistor of claim 1, further comprising:
a buried layer on the semiconductor substrate under the first well region, the buried layer having the second type of conductivity.

### Claim 8 (depends on 7)

The transistor of claim 7, wherein the buried layer has a first portion with a first dopant concentration and a second portion with a second dopant concentration, the first dopant concentration being greater than the second dopant concentration.

### Claim 9 (depends on 8)

The transistor of claim 8, wherein the first portion of the buried layer underlies the second drain portion, and wherein the second portion of the buried layer underlies the first insulating structure and the source region.

### Claim 10

A transistor, comprising:
a gate structure having a gate dielectric layer and an overlying gate electrode layer;
a source structure disposed on a first side of the gate structure;
a drain structure disposed on a second side of the gate structure opposite the first side;
an insulating layer disposed between the drain structure and the gate structure;
a first buried layer under the drain structure wherein the first buried layer does not extend under the source structure or the gate structure, wherein the first buried layer has a dopant of a first type of conductivity at a first concentration; and
a second buried layer under the gate structure and the source structure, wherein the second buried layer has a dopant of the first type of conductivity at a second concentration, the second concentration less than the first concentration.

### Claim 11 (depends on 10)

The transistor of claim 10, further comprising: a n-drift well over the first buried layer and the second buried layer; and a p-body well over the first buried layer and the second buried layer.

### Claim 12 (depends on 10)

The transistor of claim 10, wherein the drain structure includes a first drain region and a second drain region, the first and second drain regions separated by a first distance.

### Claim 13 (depends on 12)

The transistor of claim 12, wherein the first buried layer underlies the first drain region and not the second drain region.

### Claim 14 (depends on 12)

The transistor of claim 12, wherein another insulating layer is disposed in the first distance.

### Claim 15 (depends on 12)

The transistor of claim 12, further comprising: an anti-punch through layer under the second drain region of the drain structure.

### Claim 16

A transistor, comprising:
a semiconductor substrate having a first type of conductivity;
a first well region having a second type of conductivity and formed over the semiconductor substrate;
a second well region in the first well region and having the first type of conductivity, the second well region having a U-shape in a cross section and extending from a source region to a first insulating structure disposed on the semiconductor substrate adjacent a drain region, and the cross section is taken in a direction perpendicular to a top surface of the semiconductor substrate;
a second insulating structure over the first well region and at least a portion of the U-shape of the second well region and not contacting the second well region;
a gate structure between the source region and the drain region;
the drain region across the second insulating structure from the gate structure, the drain region comprising a first drain portion between the first insulating structure and the second insulating structure and a second drain portion across the first insulating structure from the first drain portion; and
the source region disposed on a side of the gate structure opposite from the drain region.

### Claim 17 (depends on 16)

The transistor of claim 16, wherein the gate structure and the drain region have one of a conic section shape and a catenary shape in a top view.

### Claim 18 (depends on 16)

The transistor of claim 16, wherein the first drain portion and the second drain portion differ in dopant conductivity type.

### Claim 19 (depends on 16)

The transistor of claim 16, wherein an anti-punch through layer is disposed under the first drain portion.

### Claim 20 (depends on 16)

The transistor of claim 16, wherein the gate structure is disposed partially on the first insulating structure.