# US 10,121,889 B2 · High voltage semiconductor device

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- Number: US 10,121,889 B2
- Document ID: US10121889B2
- Status: Granted
- Kind: B2
- Application number: 14/472,529
- Filed: 2014-08-29
- Published: 2016-03-03
- Granted: 2018-11-06
- Earliest claimed: 2014-08-29
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd.
- Inventors: Ching-Lin Chan; Cheng-Chi Lin; Shyi-Yuan Wu
- Web page: https://patentgrep.com/patent/US10121889B2

## CPC

- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 12/01: Manufacture or treatment
- H10D 12/411: {Insulated-gate bipolar transistors [IGBT]}
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/378: {Contact regions to the substrate regions}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A high voltage semiconductor device including a P type substrate, a high voltage N type well, a first P type well, a drift region, and a P type doping layer is provided. The high voltage N type well and the P type doping layer, which is formed in a region located below the first P type well and the drift region, are formed in the P type substrate. The first P type well is formed in the high voltage N type well. A bottom of the first P type well and a bottom of the P type doping layer are separated from a surface of the P type substrate by a first depth and a second depth larger than the first depth, respectively. The drift region is formed in the high voltage N type well and extending down from the surface of the P type substrate.

## Claims

### Claim 1

A high voltage semiconductor device, comprising:
a P type substrate;
a high voltage N type well formed in the P type substrate;
a first P type well formed in the high voltage N type well, a bottom of the first P type well being separated from a surface of the P type substrate by a first depth;
a source region and a drain region formed in the P type substrate, the source region is in the first P type well;
a field oxide formed on the P type substrate and located between the source region and the drain region;
a drift region formed in the high voltage N type well, wherein the drift region extends down from the surface of the P type substrate, located under the field oxide and between the source region and the drain region; and
a P type doping layer formed in the P type substrate, a bottom of the P type doping layer being separated from the surface of the P type substrate by a second depth, wherein the second depth is larger than the first depth, the P type doping layer is formed in a region located below the first P type well and the drift region, the P type doping layer is fully located under a middle region between the first P type well and the drift region, and the P type doping layer is separated from the first P type well which comprises the source region.

### Claim 2 (depends on 1)

The high voltage semiconductor device according to claim 1, wherein the P type doping layer is a P type buried layer.

### Claim 3 (depends on 1)

The high voltage semiconductor device according to claim 1, wherein the P type doping layer comprises a plurality of P type doping segments separated from one another.

### Claim 4 (depends on 1)

The high voltage semiconductor device according to claim 1, wherein a current path is formed between the source region and the drain region.

### Claim 5 (depends on 4)

The high voltage semiconductor device according to claim 4, further comprising:
a gate structure formed above the current path between the source region and the drain region.

### Claim 6 (depends on 1)

The high voltage semiconductor device according to claim 1, further comprising:
a second P type well formed in the P type substrate and adjacent to the high voltage N type well; and
a bulk region formed in the second P type well.

### Claim 7 (depends on 1)

The high voltage semiconductor device according to claim 1, further comprising:
a P type top doping layer formed in the high voltage N type well and corresponding to where the drift region is located at; and
an N type doping layer formed in the P type top doping layer.

### Claim 8

A high voltage semiconductor device, comprising:
a P type substrate;
a high voltage N type well formed in the P type substrate;
a first P type well formed in the high voltage N type well, a bottom of the first P type well being separated from a surface of the P type substrate by a first depth;
a N type heavily doping region and a P type heavily doping region formed in the P type substrate, wherein the N type heavily doping region is formed in the first P type well;
a field oxide formed on the P type substrate and located between the N type heavily doping region and the P type heavily doping region;
a drift region formed in the high voltage N type well, wherein the drift region extends down from the surface of the P type substrate, located under the field oxide and between the N type heavily doping region and the P type heavily doping region; and
a P type doping layer formed in the P type substrate, a bottom of the P type doping layer being separated from the surface of the P type substrate by a second depth, wherein the second depth is larger than the first depth, the P type doping layer is formed in a region located below the first P type well and the drift region, the P type doping layer is fully located under a middle region between the first P type well and the drift region, and the P type doping layer is separated from the first P type well which comprises the N type heavily doping region.

### Claim 9 (depends on 8)

The high voltage semiconductor device according to claim 8, wherein the P type doping layer is a P+ buried layer.

### Claim 10 (depends on 8)

The high voltage semiconductor device according to claim 8, wherein the P type doping layer comprises a plurality of P type doping segments separated from one another.

### Claim 11

A high voltage semiconductor device, comprising:
a P type substrate;
a high voltage N type well formed in the P type substrate;
a first P type well formed in the high voltage N type well, a bottom of the first P type well being separated from a surface of the P type substrate by a first depth;
a source region and a drain region formed in the P type substrate, the source region is an N type heavily doping region and formed in the first P type well;
a field oxide formed on the P type substrate and located between the source region and the drain region;
a drift region formed in the high voltage N type well, wherein the drift region extends down from the surface of the P type substrate, located under the field oxide and between the source region and the drain region;
a gate structure formed above the high voltage N type well, wherein the source region is electrically connected to the gate structure; and
a P type doping layer formed in the P type substrate, a bottom of the P type doping layer being separated from the surface of the P type substrate by a second depth, wherein the second depth is larger than the first depth, the P type doping layer is formed in a region located below the first P type well and the drift region, the P type doping layer is fully located under a middle region between the first P type well and the drift region, and the P type doping layer is separated from the first P type well which comprises the source region.

### Claim 12 (depends on 11)

The high voltage semiconductor device according to claim 11, wherein the P type doping layer is a P+ buried layer.

### Claim 13 (depends on 11)

The high voltage semiconductor device according to claim 11, wherein the P type doping layer comprises a plurality of P type doping segments separated from one another.