# US 10,121,888 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 10,121,888 B2
- Document ID: US10121888B2
- Status: Granted
- Kind: B2
- Application number: 15/640,500
- Filed: 2017-07-01
- Published: 2018-03-29
- Granted: 2018-11-06
- Earliest claimed: 2016-09-23
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Tetsuji Togami
- Web page: https://patentgrep.com/patent/US10121888B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 62/158: {Dispositions}
- H10D 62/159: {Shapes}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/839: {comprising VDMOS}
- H10D 89/10: Integrated device layouts
- H10P 50/642: {Chemical etching}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 20/0698: {Local interconnections}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 72/019: {of bond pads}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7422: {used to protect an active side of a device or wafer}
- H10W 72/0198: {batch processes}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a method of manufacturing a semiconductor device to improve the manufacturing yield of the semiconductor device. The manufacturing method includes the steps of: forming a groove extending in a first direction (y direction) across a first power transistor formation region and a second power transistor formation region, in a back surface of a semiconductor wafer; filling the groove with a conductor film by forming the conductor film on the back surface in which the groove is formed; and exposing the back surface of the semiconductor wafer by removing a portion of the conductor film.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, having the steps of:
(a) providing a semiconductor wafer having a plurality of chip regions and a cutting region located between the plurality of chip regions, the semiconductor wafer having a front surface and a back surface opposite the front surface,
wherein each of the plurality of chip regions has:
a first power transistor formation region in which a first power transistor is formed; and
a second power transistor formation region in which a second power transistor reversely coupled in series to the first power transistor is formed, and
wherein a first source of the first power transistor, a first gate of the first power transistor, a second source of the second power transistor and a second gate are respectively formed at positions closer to the front surface than the back surface;
(b) after the step (a), forming a drain electrode embedded inside of a groove formed in the back surface of the semiconductor wafer, and electrically coupled to each of a first drain of the first power transistor and a second drain of the second power transistor; and
(c) after the step (b), separating the plurality of chip regions from each other by cutting the cutting region of the semiconductor wafer,
wherein the step (b) has the steps of:
(b1) forming the groove in the back surface such that the groove is extended in a first direction across the first power transistor formation region and the second power transistor formation region in plan view;
(b2) after the step (b1), filling the inside of the groove with a conductor film by forming the conductor film on the back surface in which the groove is formed; and
(b3) after the step (b2), exposing the back surface of the semiconductor wafer by removing a portion of the conductor film that is located outside the groove.

### Claim 2 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1,
wherein the cutting region is included in the back surface exposed from the conductor film, in a plan view.

### Claim 3 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1,
wherein the semiconductor wafer has:
a substrate layer including the back surface; and
an epitaxial layer formed over the substrate layer,
wherein the step (b1) forms the groove in the back surface of the semiconductor wafer in such a way that the bottom surface of the groove is located within the substrate layer.

### Claim 4 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1,
wherein pluralities of grooves are present in the back surface of the semiconductor wafer.

### Claim 5 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1,
wherein the aspect ratio of the groove is one or more.

### Claim 6 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1,
wherein the semiconductor wafer has:
a substrate layer including the back surface; and
an epitaxial layer formed over the substrate layer,
wherein the first power transistor has:
a first channel layer formed in the epitaxial layer;
a first source contacting the first channel layer; and
a first body contact plug contacting the first source and reaching the first channel layer, and
wherein the second power transistor has:
a second channel layer formed in the epitaxial layer;
a second source contacting the second channel layer, and
a second body contact plug contacting the second source and reaching the second channel layer.

### Claim 7 (depends on 6)

The method of manufacturing a semiconductor device according to claim 6,
wherein the first body contact plug and the second body contact plug each extend in a second direction intersecting the first direction.

### Claim 8 (depends on 6)

The method of manufacturing a semiconductor device according to claim 6,
wherein the first body contact plug and the second body contact plug each extend in the first direction.

### Claim 9 (depends on 6)

The method of manufacturing a semiconductor device according to claim 6,
wherein the width of the groove in the second direction intersecting the first direction is greater than the width of the first body contact plug in a direction intersecting the extending direction of the first body contact plug.

### Claim 10 (depends on 6)

The method of manufacturing a semiconductor device according to claim 6,
wherein the groove includes the first body contact plug in a plan view.