# US 10,121,887 B2 · Insulated gate semiconductor device and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,887 B2 - Document ID: US10121887B2 - Status: Granted - Kind: B2 - Application number: 14/618,571 - Filed: 2015-02-10 - Published: 2015-06-18 - Granted: 2018-11-06 - Earliest claimed: 2011-02-17 - Assignees: Semiconductor Components Industries, LLC - Applicants: Semiconductor Components Industries, LLC - Inventors: Haruyoshi Yagi; Manabu Yajima - Web page: https://patentgrep.com/patent/US10121887B2 ## CPC - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 1/47: Resistors having no potential barriers - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 30/665: {having edge termination structures} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 64/517: {characterised by the conducting layers} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/141: {VDMOS having built-in components} - H10D 84/148: {the built-in components being breakdown diodes, e.g. Zener diodes} - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10D 89/611: {using diodes as protective elements} - H10D 89/911: {using passive elements as protective elements} - H10W 20/484: {Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes} - H10D 8/80: PNPN diodes, e.g. Shockley diodes or break-over diodes - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10D 62/126: {Top-view geometrical layouts of the regions or the junctions} - H10D 89/10: Integrated device layouts - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/9223: {with redistribution layers [RDL]} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract In a MOSFET, the lead parts of gate lead wiring that lead out a gate electrode on the periphery of a substrate constitute a non-operative region where it is impossible to dispose a MOSFET transistor cell (C) that will function as efficiently as inside an element region. If the gate lead wiring is disposed along the four edges of a chip, for example, the area of the non-operative region increases, limiting the extent to which the surface area of the element region can be enlarged and the chip surface area reduced. In the present invention, gate lead wiring and a conductor, which is connected to the gate lead wiring and a protection diode, are disposed in a non-curved, linear configuration along one edge of a chip. In addition, a first gate electrode layer that extends superimposed on the gate lead wiring and the conductor, and connects the gate lead wiring and the conductor to the protection diode, has no more than one curved part. Furthermore, the protection diode is disposed adjacent to the conductor or the gate lead wiring, and a portion of the protection diode is disposed near a gate pad. ## Claims ### Claim 1 A semiconductor device comprising: a first semiconductor layer of a first general conductivity type and provided in the form of a rectangle having long sides and short sides in a plan view; an element region in a surface of the first semiconductor layer and having a transistor cell of an insulated-gate semiconductor element arranged therein; a gate pad portion on the element region and coupled to a gate electrode of the transistor cell; a gate lead wiring electrically coupling the gate electrode to the gate pad portion, wherein the gate lead wiring comprises: lead portions disposed within the first semiconductor layer, directly connected to the gate electrode, and leading out the gate electrode to a peripheral portion of the first semiconductor layer that is outside of the element region, wherein the lead portions are provided as generally parallel and spaced-apart stripes in the plan view, wherein the stripes are parallel to the long sides in the plan view; and a coupling portion connecting the lead portions together outside of the element region on the peripheral portion, wherein the coupling portion is parallel to the short sides in the plan view; a conductor connected to the coupling portion on the peripheral portion, wherein the coupling portion and the conductor are provided along one short side of the first semiconductor layer linearly without bending; and a protection diode connected between a source electrode and the gate electrode of the transistor cell, wherein the conductor is further electrically coupled to the protection diode, and wherein the protection diode does not overlap the gate pad portion and is located outside of the element region, and wherein the protection diode is in the form of a rectangle having long sides and short sides in the plan view, and wherein the long sides of the protection diode are disposed to be parallel to the long sides of the first semiconductor layer and orthogonal to the coupling portion in the plan view. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the protection diode is disposed in a corner portion of the semiconductor device. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the protection diode, the coupling portion, and the conductor are arranged adjacently; and wherein the lead portions are provided along only the one short side. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the protection diode is disposed along one long side. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the protection diode is disposed in close proximity to the gate pad portion. ### Claim 6 (depends on 1) The semiconductor device according to claim 1 further comprising a first gate electrode layer extending on the coupling portion and the conductor and being connected to one end of the protection diode, wherein the first gate electrode layer bends at most at one portion. ### Claim 7 (depends on 6) The semiconductor device according to claim 6 further comprising a second gate electrode layer connected to the first gate electrode layer on the protection diode is provided, wherein the gate pad portion is a portion of the second gate electrode layer. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the protection diode comprises a bidirectional diode provided with more than one pn junction. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the bidirectional diode comprises two pn junctions provided concentrically. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the protection diode is provided in a polycrystalline semiconductor layer. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the gate electrode has a stripe shape and extends along the long sides. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein: the lead portions comprise polycrystalline semiconductor material buried in trenches provided in the first semiconductor layer; and the lead portions are provided generally perpendicular to the one short side. ### Claim 13 (depends on 1) The semiconductor device of claim 1, wherein the conductor comprises a polycrystalline semiconductor resistor. ### Claim 14 A method of forming a semiconductor device comprising: providing a first semiconductor layer of a first general conductivity type and provided in the form of a rectangle having long sides and short sides in a plan view; providing an element region in a surface of the first semiconductor layer and having a transistor cell of an insulated-gate semiconductor element arranged therein; forming a gate pad portion on the element region and connected to a gate electrode of the transistor cell; forming a gate lead wiring electrically coupling the gate electrode to the gate pad portion, wherein the gate lead wiring comprises: lead portions disposed within the first semiconductor layer, directly connected to the gate electrode, and leading out the gate electrode to a peripheral portion of the first semiconductor later that is outside of the element region, wherein the lead portions are provided as generally parallel and spaced-apart stripes in the plan view, wherein the stripes are parallel to the long sides in the plan view; and a coupling portion connecting the lead portions together outside of the element region on the peripheral portion; forming a conductor on the peripheral portion and connected to the coupling portion, wherein the coupling portion and the conductor are provided along one side of the first semiconductor layer of the first general conductivity type linearly without bending in the plan view; and forming a protection diode connected between a source electrode and the gate electrode of the transistor cell, wherein the conductor is further electrically coupled to the protection diode, and wherein the protection diode does not overlap the gate pad portion and is located outside of the element region, and wherein the protection diode is in the form of a rectangle having long sides and short sides in the plan view, and wherein the long sides of the protection diode are disposed to be parallel to the long sides of the first semiconductor layer and orthogonal to the coupling portion in the plan view. ### Claim 15 (depends on 14) The method of claim 14, wherein forming the protection diode comprises disposed the protection diode in a corner portion of the semiconductor device. ### Claim 16 (depends on 15) The method of claim 15 further comprising forming a first gate electrode layer extending on the coupling portion and the conductor and being connected to one end of the protection diode, wherein the first gate electrode layer bends at most at one portion, and wherein forming the gate lead wiring comprising forming the lead portion along only the one side. ### Claim 17 (depends on 14) The method of claim 14, wherein the forming gate lead wiring comprises: forming the lead portions comprising doped polycrystalline semiconductor material buried in trenches provided in the first semiconductor layer; and forming the coupling portion comprising doped polycrystalline semiconductor material, wherein coupling portion has a configuration of extending the lead portions on a surface of the first semiconductor layer. ### Claim 18 A method of forming an insulated-gate semiconductor device comprising: providing a first semiconductor layer of a first general conductivity type and provided in the form of a rectangle having long sides and short sides in a plan view; providing an element region in a surface of the first semiconductor layer of the first general conductivity type, and having a transistor cell of an insulated-gate semiconductor element arranged therein; forming a gate pad portion on the element region and connected to a gate electrode of the transistor cell; forming a protection diode connected between a source electrode and the gate electrode of the transistor cell; forming a gate lead wiring comprising: lead portions disposed within the first semiconductor layer, directly connected to the gate electrode, and leading out the gate electrode to the outside of the element region to the peripheral portion of the first semiconductor layer that is outside of the element region, wherein the lead portions are provided as generally parallel and spaced-apart stripes in the plan view, wherein the stripes are parallel to the long sides in the plan view; and a coupling portion directly contacting and connecting the lead portions together on the peripheral portion; and forming a conductor connected to the coupling portion and the protection diode, wherein the coupling portion and the conductor are provided along one side of the first semiconductor layer of the first general conductivity type linearly without bending in the plan view, wherein: the protection diode does not overlap the gate pad portion and is located outside of the element region; the protection diode is in the form of a rectangle having long sides and short sides in the plan view; the long sides of the protection diode are disposed to be parallel to the long sides of the first semiconductor layer and orthogonal to the coupling portion in the plan view; and the protection diode is disposed in a corner portion of the semiconductor device. ### Claim 19 (depends on 18) The method of claim 18 further comprising: forming a first gate electrode layer extending on the coupling portion and the conductor and being connected to one end of the protection diode, wherein the first gate electrode layer bends at most at one portion. ### Claim 20 (depends on 19) The method of claim 19 further comprising forming a second gate electrode layer connected to the first gate electrode layer, and wherein forming the gate pad portion comprises forming the gate pad portion as a portion of the second gate electrode layer. ### Claim 21 (depends on 19) The method of claim 19, wherein forming the gate lead wiring comprises forming the lead portions along only the one side. ### Claim 22 (depends on 19) The method of claim 19, wherein forming the protection diode comprises forming a bidirectional diode provided with more than one pn junction.