# US 10,121,885 B2 · Protective insulator for HFET devices

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- Number: US 10,121,885 B2
- Document ID: US10121885B2
- Status: Granted
- Kind: B2
- Application number: 15/628,269
- Filed: 2017-06-20
- Published: 2017-10-12
- Granted: 2018-11-06
- Earliest claimed: 2016-04-11
- Assignees: Power Integrations, Inc.
- Applicants: Power Integrations, Inc.
- Inventors: Alexey Kudymov; Linlin Liu; Xiaohui Wang; Jamal Ramdani
- Web page: https://patentgrep.com/patent/US10121885B2

## CPC

- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/267: {using plasmas}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A high-voltage field effect transistor a heterojunction is disposed between the first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and a second composite passivation layer includes a second insulation layer and a second passivation layer. The first insulation layer is disposed between the first passivation layer and the second passivation layer, and the second passivation layer is disposed between the first insulation layer and the second insulation layer. A gate dielectric disposed between the second semiconductor material and the first passivation layer. A gate electrode is disposed above the gate dielectric. A first gate field plate is disposed between the first passivation layer and the second passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material.

## Claims

### Claim 1

A high-voltage field effect transistor (HFET), comprising:
a first semiconductor material, a second semiconductor material, and a heterojunction, wherein the heterojunction is disposed between the first semiconductor material and the second semiconductor material;
a plurality of composite passivation layers, wherein a first composite passivation layer in the plurality of composite passivation layers includes a first insulation layer and a first passivation layer, wherein a second composite passivation layer in the plurality of composite passivation layers includes a second insulation layer and a second passivation layer, wherein the first insulation layer is disposed between the first passivation layer and the second passivation layer, and the second passivation layer is disposed between the first insulation layer and the second insulation layer, wherein the first insulation layer and the second insulation layer have wider bandgaps than the first passivation layer and the second passivation layer, and wherein the plurality of composite passivation layers further comprises a third composite passivation layer including a third insulation layer and a third passivation layer, wherein the second insulation layer is disposed between the second passivation layer and the third passivation layer;
a gate dielectric disposed between the second semiconductor material and the first passivation layer;
a gate electrode disposed above the gate dielectric;
a first gate field plate disposed between the first passivation layer and the second passivation layer; and
a source electrode and a drain electrode, wherein the source electrode and drain electrode are coupled to the second semiconductor material.

### Claim 2 (depends on 1)

The HFET of claim 1, wherein the first gate field plate is coupled to the gate electrode.

### Claim 3 (depends on 1)

The HFET of claim 1, further including a source field plate coupled to the source electrode, wherein the source field plate is disposed above the second insulation layer and the first gate field plate is disposed between the first insulation layer and the second passivation layer.

### Claim 4 (depends on 3)

The HFET of claim 3, wherein lateral bounds of the first insulation layer are substantially coextensive with lateral bounds of the source field plate, and wherein lateral bounds of the second insulation layer are substantially coextensive with the lateral bounds of the source field plate.

### Claim 5 (depends on 1)

The HFET of claim 1, further comprising a second gate field plate disposed between the second passivation layer and the third passivation layer.

### Claim 6 (depends on 1)

The HFET of claim 1, further comprising:
a fourth passivation layer wherein the third insulation layer is disposed between the third passivation layer and the fourth passivation layer;
a source field plate coupled to the source electrode, and
a second gate field plate coupled to the first gate field plate, wherein the second gate field plate is disposed between the second passivation layer and the third passivation layer, and wherein the source field plate is disposed between the third passivation layer and the fourth passivation layer.

### Claim 7 (depends on 6)

The HFET of claim 6, further comprising a third gate field plate coupled to the second gate field plate and disposed between the third passivation layer and fourth passivation layer.

### Claim 8 (depends on 6)

The HFET of claim 6, wherein lateral bounds of the first insulation layer are substantially coextensive with lateral bounds of the first gate field plate, wherein lateral bounds of the second insulation layer are substantially coextensive with lateral bounds of the second gate field plate, and wherein lateral bounds of the third insulation layer are substantially coextensive with the lateral bounds of the source field plate.

### Claim 9 (depends on 1)

The HFET of claim 1, wherein the gate dielectric and the first insulation layer in the plurality of composite passivation layers include a same material composition.

### Claim 10 (depends on 1)

The HFET of claim 1, wherein the gate dielectric and the first insulation layer in the plurality of composite passivation layers are different material compositions.

### Claim 11 (depends on 1)

The HFET of claim 1, wherein the first passivation layer and the second passivation layer in the plurality of composite passivation layers are nitride based layers.

### Claim 12 (depends on 1)

The HFET of claim 1, wherein the first insulation layer and the second insulation layer are oxide based layers.

### Claim 13 (depends on 1)

The HFET of claim 1, wherein the first insulation layer and the second insulation layer are nitride based layers.

### Claim 14 (depends on 1)

The HFET of claim 1, wherein insulation layers in the plurality of composite passivation layers are disposed to prevent charging of passivation layers in the plurality of composite passivation layers.

### Claim 15 (depends on 1)

The HFET of claim 1, wherein the drain electrode extends from the second semiconductor material through at least one of the plurality of composite passivation layers.

### Claim 16 (depends on 1)

The HFET of claim 1, wherein lateral bounds of the first insulation layer are substantially coextensive with lateral bounds of the first passivation layer, and wherein lateral bounds of the second insulation layer are substantially coextensive with the lateral bounds of the second passivation layer.

### Claim 17 (depends on 1)

The HFET of claim 1, wherein the first insulation layer is disposed above the first passivation layer and the second insulation layer is disposed above the second passivation layer.