# US 10,121,883 B2 · Manufacturing method of top gate thin-film transistor

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- Number: US 10,121,883 B2
- Document ID: US10121883B2
- Status: Granted
- Kind: B2
- Application number: 15/121,040
- Filed: 2016-07-15
- Published: 2018-07-12
- Granted: 2018-11-06
- Earliest claimed: 2016-06-22
- Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Inventors: Yong Deng
- Web page: https://patentgrep.com/patent/US10121883B2

## CPC

- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10P 34/42: with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a manufacturing method of a top gate thin-film transistor, which includes forming a reducing metal layer on an oxide semiconductor layer and applying laser annealing to reduce the oxide semiconductor layer that is covered with the reducing metal layer to conductors to respectively form a source contact zone and a drain contact zone, such that the source contact zone and the drain contact zone that have been reduced to conductors are used to respectively contact a source electrode and a drain electrode thereby greatly reducing the contact resistance of the source electrode and the drain electrode and improving the performance of a top gate thin-film transistor. The manufacturing process is simple.

## Claims

### Claim 1

A manufacturing method of a top gate thin-film transistor, comprising the following steps:
Step 1: providing a base plate, forming a buffer layer on the base plate, and forming an oxide semiconductor layer on the buffer layer;
Step 2: forming a gate insulation layer and a gate electrode on the oxide semiconductor layer in a manner of being stacked in sequence from bottom to top, such that the gate insulation layer and the gate electrode cover a middle zone of the oxide semiconductor layer with two ends of the oxide semiconductor layer exposed;
Step 3: forming a reducing metal layer on the two exposed ends of the oxide semiconductor layer;
Step 4: subjecting the oxide semiconductor layer that is covered with the reducing metal layer to laser annealing in order to reduce the oxide semiconductor layer that is covered with the reducing metal layer to conductors that form a source contact zone and a drain contact zone respectively located at two ends of the oxide semiconductor layer;
Step 5: subsequently forming an interlayer insulation layer on the gate electrode, the source contact zone, and the drain contact zone and a first via and a second via extending through the interlayer insulation layer, such that the first via and the second via respectively expose the source contact zone and the drain contact zone; and
Step 6: forming a source electrode and a drain electrode on the interlayer insulation layer, such that the source electrode and the drain electrode are respectively set in contact with the source contact zone and the drain contact zone through the first via and the second via;
wherein the reducing metal layer comprises two parts that are respectively formed on the two exposed ends of the oxide semiconductor and are separate from each other such that laser annealing is applied only to the two exposed ends of he oxide semiconductor layer.

### Claim 2 (depends on 1)

The manufacturing method of a top gate thin-film transistor as claimed in claim 1, wherein in Step 3, the reducing metal layer is formed of a material comprising manganese or aluminum.

### Claim 3 (depends on 1)

The manufacturing method of a top gate thin-film transistor as claimed in claim 1, wherein in Step 3, the reducing metal layer has a thickness less than 100 Å.

### Claim 4 (depends on 1)

The manufacturing method of a top gate thin-film transistor as claimed in claim 1, wherein in Step 3, the reducing metal layer is formed with physical vapor deposition.

### Claim 5 (depends on 1)

The manufacturing method of a top gate thin-film transistor as claimed in claim 1, wherein the oxide semiconductor layer is formed of a material comprising indium gallium zinc oxide (IGZO).

### Claim 6 (depends on 1)

The manufacturing method of a top gate thin-film transistor as claimed in claim 1, wherein the gate electrode, the source electrode, and the drain electrode are formed of a material comprising molybdenum.

### Claim 7 (depends on 1)

The manufacturing method of a top gate thin-film transistor as claimed in claim 1, wherein in Step 2, a dry etching operation is applied to form the gate insulation layer and the gate electrode.

### Claim 8 (depends on 1)

The manufacturing method of a top gate thin-film transistor as claimed in claim 1, wherein Step 3 further comprises forming the reducing metal layer on the gate electrode and the buffer layer, such that a portion of the reducing metal layer on the gate electrode is separated from a portion of the reducing metal layer on the oxide semiconductor layer; and
in Step 5, the interlayer insulation layer covers the portion of the reducing metal layer on the gate electrode.

### Claim 9 (depends on 8)

The manufacturing method of a top gate thin-film transistor as claimed in claim 8, wherein in Step 3, a portion of the reducing metal layer on the oxide semiconductor layer is separated from a portion of the reducing metal layer on the buffer layer.

### Claim 10 (depends on 1)

The manufacturing method of a top gate thin-film transistor as claimed in claim 1, wherein the buffer layer, the gate insulation layer, and the interlayer insulation layer are formed of a material comprising one or a stacked combination of multiple ones of silicon oxide and silicon nitride.

### Claim 11

A manufacturing method of a top gate thin-film transistor, comprising the following steps:
Step 1: providing a base plate, forming a buffer layer on the base plate, and forming an oxide semiconductor layer on the buffer layer;
Step 2: forming a gate insulation layer and a gate electrode on the oxide semiconductor layer in a manner of being stacked in sequence from bottom to top, such that the gate insulation layer and the gate electrode cover a middle zone of the oxide semiconductor layer with two ends of the oxide semiconductor layer exposed;
Step 3: forming a reducing metal layer on the two exposed ends of the oxide semiconductor layer;
Step 4: subjecting the oxide semiconductor layer that is covered with the reducing metal layer to laser annealing in order to reduce the oxide semiconductor layer that is covered with the reducing metal layer to conductors that form a source contact zone and a drain contact zone respectively located at two ends of the oxide semiconductor layer;
Step 5: subsequently forming an interlayer insulation layer on the gate electrode, the source contact zone, and the drain contact zone and a first via and a second via extending through the interlayer insulation layer, such that the first via and the second via respectively expose the source contact zone and the drain contact zone; and
Step 6: forming a source electrode and a drain electrode on the interlayer insulation layer, such that the source electrode and the drain electrode are respectively set in contact with the source contact zone and the drain contact zone through the first via and the second via;
wherein the reducing metal layer comprises two parts that are respectively formed on the two exposed ends of the oxide semiconductor and are separate from each other such that laser annealing is applied only to the two exposed ends of the oxide semiconductor layer;
wherein in Step 3, the reducing metal layer is formed of a material comprising manganese or aluminum; and
wherein in Step 3, the reducing metal layer has a thickness less than 100 Å.

### Claim 12 (depends on 11)

The manufacturing method of a top gate thin-film transistor as claimed in claim 11, wherein in Step 3, the reducing metal layer is formed with physical vapor deposition.

### Claim 13 (depends on 11)

The manufacturing method of a top gate thin-film transistor as claimed in claim 11, wherein the oxide semiconductor layer is formed of a material comprising indium gallium zinc oxide (IGZO).

### Claim 14 (depends on 11)

The manufacturing method of a top gate thin-film transistor as claimed in claim 11, wherein the gate electrode, the source electrode, and the drain electrode are formed of a material comprising molybdenum.

### Claim 15 (depends on 11)

The manufacturing method of a top gate thin-film transistor as claimed in claim 11, wherein in Step 2, a dry etching operation is applied to form the gate insulation layer and the gate electrode.

### Claim 16 (depends on 11)

The manufacturing method of a top gate thin-film transistor as claimed in claim 11, wherein Step 3 further comprises forming the reducing metal layer on the gate electrode and the buffer layer, such that a portion of the reducing metal layer on the gate electrode is separated from a portion of the reducing metal layer on the oxide semiconductor layer; and
in Step 5, the interlayer insulation layer covers the portion of the reducing metal layer on the gate electrode.

### Claim 17 (depends on 16)

The manufacturing method of a top gate thin-film transistor as claimed in claim 16, wherein in Step 3, a portion of the reducing metal layer on the oxide semiconductor layer is separated from a portion of the reducing metal layer on the buffer layer.

### Claim 18 (depends on 11)

The manufacturing method of a top gate thin-film transistor as claimed in claim 11, wherein the buffer layer, the gate insulation layer, and the interlayer insulation layer are formed of a material comprising one or a stacked combination of multiple ones of silicon oxide and silicon nitride.