# US 10,121,882 B1 · Gate line plug structures for advanced integrated circuit structure fabrication

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- Number: US 10,121,882 B1
- Document ID: US10121882B1
- Status: Granted
- Kind: B1
- Application number: 15/859,353
- Filed: 2017-12-30
- Granted: 2018-11-06
- Earliest claimed: 2017-11-30
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Byron Ho; Michael L. Hattendorf; Christopher P. Auth
- Web page: https://patentgrep.com/patent/US10121882B1

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10B 10/12: {comprising a MOSFET load element}
- H10D 1/47: Resistors having no potential barriers
- H10D 1/474: {comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6213: {having rounded corners}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 30/794: {comprising conductive materials, e.g. silicided source, drain or gate electrodes}
- H10D 30/795: {being in lateral device isolation regions, e.g. STI}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/834: further characterised by the dopants
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/01354: {passivation or protection of the electrode, e.g. using re-oxidation}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 64/689: {having ferroelectric layers}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 89/10: Integrated device layouts
- H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/418: {the conductive layers comprising transition metals}
- H10P 50/282: {of inorganic materials}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/071: {of dielectric parts thereof}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/43: Layouts of interconnections
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/4437: {the principal metal being a transition metal}
- H10W 20/48: Insulating materials thereof
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 30/791: {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 72/851: {Dispositions of multiple connectors or interconnections}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a first silicon fin having a longest dimension along a first direction;
a second silicon fin having a longest dimension along the first direction;
an insulator material between the first silicon fin and the second silicon fin;
a gate line over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug;
a trench contact over the first silicon fin and over the second silicon fin along the second direction at the first side of the gate line, the trench contact continuous over the insulator material at a location laterally adjacent to the dielectric plug; and
a dielectric spacer laterally between the trench contact and the first side of the gate line, the dielectric spacer continuous along the first side of the gate line and the dielectric plug, and the dielectric spacer having a width laterally adjacent to the dielectric plug thinner than a width laterally adjacent to the first side of the gate line.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, further comprising:
a second trench contact over the first silicon fin and over the second silicon fin along the second direction at the second side of the gate line, the second trench contact continuous over the insulator material at a location laterally adjacent to the dielectric plug.

### Claim 3 (depends on 2)

The integrated circuit structure of claim 2, further comprising:
a second dielectric spacer laterally between the second trench contact and the second side of the gate line, the second dielectric spacer continuous along the second side of the gate line and the dielectric plug, and the second dielectric spacer having a width laterally adjacent to the dielectric plug thinner than a width laterally adjacent to the second side of the gate line.

### Claim 4 (depends on 1)

The integrated circuit structure of claim 1, wherein the gate line comprises a high-k gate dielectric layer, a gate electrode, and a dielectric cap layer.

### Claim 5 (depends on 1)

The integrated circuit structure of claim 1, wherein the dielectric plug comprises a same material as the dielectric spacer but is discrete from the dielectric spacer.

### Claim 6

An integrated circuit structure, comprising:
a first silicon fin having a longest dimension along a first direction;
a second silicon fin having a longest dimension along the first direction;
an insulator material between the first silicon fin and the second silicon fin;
a gate line over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug;
a trench contact over the first silicon fin and over the second silicon fin along the second direction at the first side of the gate line, the trench contact continuous over the insulator material at a location laterally adjacent to the dielectric plug; and
a dielectric spacer laterally between the trench contact and the first side of the gate line, the dielectric spacer along the first side of the gate line but not along the dielectric plug, wherein the trench contact has a width laterally adjacent to the dielectric plug thinner than a width laterally adjacent to the dielectric spacer.

### Claim 7 (depends on 6)

The integrated circuit structure of claim 6, further comprising:
a second trench contact over the first silicon fin and over the second silicon fin along the second direction at the second side of the gate line, the second trench contact continuous over the insulator material at a location laterally adjacent to the dielectric plug.

### Claim 8 (depends on 7)

The integrated circuit structure of claim 7, further comprising:
a second dielectric spacer laterally between the second trench contact and the second side of the gate line, the second dielectric spacer along the second side of the gate line but not along the dielectric plug, wherein the second trench contact has a width laterally adjacent to the dielectric plug thinner than a width laterally adjacent to the second dielectric spacer.

### Claim 9 (depends on 6)

The integrated circuit structure of claim 6, wherein the gate line comprises a high-k gate dielectric layer, a gate electrode, and a dielectric cap layer.

### Claim 10 (depends on 6)

The integrated circuit structure of claim 6, wherein the dielectric plug comprises a same material as the dielectric spacer but is discrete from the dielectric spacer.

### Claim 11

A method of fabricating an integrated circuit structure, the method comprising:
forming a plurality of gate lines over a plurality of semiconductor fins and over a trench isolation structure between the semiconductor fins, individual ones of the gate lines having dielectric sidewall spacers;
removing one of the plurality of gate lines to form a trench, wherein the dielectric sidewall spacers adjacent the one of the plurality of gate lines are eroded during the removing, and wherein residual portions of the one of the plurality of gate lines remain at a bottom of the trench following the removing;
forming a hardmask on upper portions of the trench;
removing the residual portions of the one of the plurality of gate lines from the bottom of the trench;
removing the hardmask; and
filling the trench with a dielectric plug material.

### Claim 12 (depends on 11)

The method of claim 11, wherein the removing the residual portions of the one of the plurality of gate lines from the bottom of the trench comprises removing polycrystalline silicon portions.

### Claim 13 (depends on 11)

The method of claim 11, wherein the removing the one of the plurality of gate lines to form the trench and the removing the residual portions of the one of the plurality of gate lines from the bottom of the trench comprises using a same etch chemistry.

### Claim 14 (depends on 11)

The method of claim 11, wherein the hardmask protects the dielectric sidewall spacers from further erosion during the removing the residual portions of the one of the plurality of gate lines from the bottom of the trench.

### Claim 15 (depends on 11)

The method of claim 11, wherein filling the trench with the dielectric plug material comprises forming a dielectric plug having a tapered profile.

### Claim 16 (depends on 11)

The method of claim 11, further comprising:
replacing remaining ones of the plurality of gate lines with a permanent gate structure.

### Claim 17

An integrated circuit structure, comprising:
a first silicon fin having a longest dimension along a first direction;
a second silicon fin having a longest dimension along the first direction;
an insulator material between the first silicon fin and the second silicon fin;
a gate line over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug;
a trench contact over the first silicon fin and over the second silicon fin along the second direction at the first side of the gate line, the trench contact continuous over the insulator material at a location laterally adjacent to the dielectric plug; and
a dielectric spacer laterally between the trench contact and the first side of the gate line, wherein an upper portion of the dielectric spacer is along the first side of the gate line but not along the dielectric plug, and an upper portion of the trench contact has a width laterally adjacent to an upper portion of the dielectric plug thinner than a width laterally adjacent to the dielectric spacer, and wherein a lower portion of the dielectric spacer is continuous along the first side of the gate line and the dielectric plug, and the lower portion of the dielectric spacer has a width laterally adjacent to the dielectric plug thinner than a width laterally adjacent to the first side of the gate line.

### Claim 18 (depends on 17)

The integrated circuit structure of claim 17, wherein the dielectric plug has a tapered profile.

### Claim 19 (depends on 17)

The integrated circuit structure of claim 17, wherein the gate line comprises a high-k gate dielectric layer, a gate electrode, and a dielectric cap layer.

### Claim 20 (depends on 17)

The integrated circuit structure of claim 17, wherein the dielectric plug comprises a same material as the dielectric spacer but is discrete from the dielectric spacer.