# US 10,121,875 B1 · Replacement gate structures for advanced integrated circuit structure fabrication

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- Number: US 10,121,875 B1
- Document ID: US10121875B1
- Status: Granted
- Kind: B1
- Application number: 15/859,354
- Filed: 2017-12-30
- Granted: 2018-11-06
- Earliest claimed: 2017-11-30
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Byron Ho; Steven Jaloviar; Jeffrey S. Leib; Michael L. Hattendorf; Christopher P. Auth
- Web page: https://patentgrep.com/patent/US10121875B1

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10B 10/12: {comprising a MOSFET load element}
- H10D 1/47: Resistors having no potential barriers
- H10D 1/474: {comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6213: {having rounded corners}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 30/794: {comprising conductive materials, e.g. silicided source, drain or gate electrodes}
- H10D 30/795: {being in lateral device isolation regions, e.g. STI}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/834: further characterised by the dopants
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/01354: {passivation or protection of the electrode, e.g. using re-oxidation}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 64/689: {having ferroelectric layers}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 89/10: Integrated device layouts
- H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/418: {the conductive layers comprising transition metals}
- H10P 50/282: {of inorganic materials}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/071: {of dielectric parts thereof}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/43: Layouts of interconnections
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/4437: {the principal metal being a transition metal}
- H10W 20/48: Insulating materials thereof
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 30/791: {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 72/851: {Dispositions of multiple connectors or interconnections}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a fin protruding from a semiconductor substrate, the fin having a lower fin portion and an upper fin portion, the upper fin portion having a top and sidewalls;
an isolation structure surrounding the lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin;
a gate dielectric layer over the top of the upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material;
a gate electrode over the gate dielectric layer over the top of the upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate electrode further over the gate dielectric layer on the semiconductor material on the portion of the top surface of the insulating material;
a first source or drain region adjacent a first side of the gate electrode; and
a second source or drain region adjacent a second side of the gate electrode, the second side opposite the first side.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the semiconductor material on the portion of the top surface of the insulating material comprises polycrystalline silicon.

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, wherein the top surface of the insulating material has a concave depression, and wherein the semiconductor material is in the concave depression.

### Claim 4 (depends on 1)

The integrated circuit structure of claim 1, wherein the isolation structure comprises a second insulating material along a bottom and sidewalls of the insulating material.

### Claim 5 (depends on 4)

The integrated circuit structure of claim 4, wherein the portion of the second insulating material along the sidewalls of the insulating material has a top surface above an uppermost surface of the insulating material.

### Claim 6 (depends on 5)

The integrated circuit structure of claim 5, wherein the top surface of the second insulating material is above an uppermost surface of the semiconductor material.

### Claim 7 (depends on 1)

The integrated circuit structure of claim 1, wherein the semiconductor material on the portion of the top surface of the insulating material does not extend beyond the gate dielectric layer.

### Claim 8 (depends on 1)

The integrated circuit structure of claim 1, further comprising:
a first dielectric spacer along the first side of the gate electrode; and
a second dielectric spacer along the second side of the gate electrode.

### Claim 9 (depends on 8)

The integrated circuit structure of claim 8, wherein the gate dielectric layer further extends along sidewalls of the first dielectric spacer and the second dielectric spacer.

### Claim 10 (depends on 1)

The integrated circuit structure of claim 1, wherein the gate electrode comprises a workfunction layer.

### Claim 11 (depends on 10)

The integrated circuit structure of claim 10, wherein the workfunction layer comprises titanium and nitrogen.

### Claim 12 (depends on 10)

The integrated circuit structure of claim 10, wherein the workfunction layer comprises titanium, aluminum, carbon and nitrogen.

### Claim 13 (depends on 10)

The integrated circuit structure of claim 10, wherein the gate electrode further comprises a conductive fill metal layer over the workfunction layer.

### Claim 14 (depends on 13)

The integrated circuit structure of claim 13, wherein the conductive fill metal layer comprises tungsten.

### Claim 15 (depends on 14)

The integrated circuit structure of claim 14, wherein the conductive fill metal layer comprises 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine.

### Claim 16

A method of fabricating an integrated circuit structure, the method comprising:
forming a fin from a semiconductor substrate, the fin having a lower fin portion and an upper fin portion, the upper fin portion having a top and sidewalls;
forming an isolation structure surrounding the lower fin portion, the isolation structure comprising an insulating material having a top surface;
forming a placeholder gate electrode over the top of the upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the placeholder gate electrode comprising a semiconductor material;
forming a first source or drain region adjacent a first side of the placeholder gate electrode and a second source or drain region adjacent a second side of the placeholder gate electrode, the second side opposite the first side;
forming an inter-layer dielectric (ILD) layer laterally adjacent the placeholder gate electrode;
etching the placeholder gate electrode from the top and sidewalls of the upper fin portion, wherein the etching is incomplete and leaves a portion of the placeholder gate electrode on a portion of the top surface of the insulating material of the isolation structure;
forming a gate dielectric layer over the top of the upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further formed on the portion of the placeholder gate electrode on the portion of the top surface of the insulating material of the isolation structure; and
forming a permanent gate electrode over the gate dielectric layer over the top of the upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the permanent gate electrode further over the gate dielectric layer on the portion of the placeholder gate electrode on the portion of the top surface of the insulating material.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
prior to forming the placeholder gate electrode, forming a placeholder gate dielectric layer; and
subsequent to etching the placeholder gate electrode, removing the placeholder gate dielectric layer.

### Claim 18 (depends on 16)

The method of claim 16, wherein the placeholder gate electrode comprises polycrystalline silicon.

### Claim 19 (depends on 16)

The method of claim 16, wherein the top surface of the insulating material of the isolation structure has a concave depression, and wherein the portion of the placeholder gate electrode is in the concave depression.

### Claim 20 (depends on 16)

The method of claim 16, wherein the isolation structure comprises a second insulating material along a bottom and sidewalls of the insulating material.

### Claim 21 (depends on 20)

The method of claim 20, wherein the portion of the second insulating material along the sidewalls of the insulating material has a top surface above at least a portion of the top surface of the insulating material.

### Claim 22 (depends on 21)

The method of claim 21, wherein the top surface of the second insulating material is above a lowermost surface of the portion of the placeholder gate electrode.

### Claim 23 (depends on 16)

The method of claim 16, wherein the portion of the placeholder gate electrode on the portion of the top surface of the insulating material does not extend beyond the gate dielectric layer.

### Claim 24 (depends on 16)

The method of claim 16, further comprising:
prior to forming the ILD layer, forming a first dielectric spacer along the first side of the placeholder gate electrode and forming a second dielectric spacer along the second side of the placeholder gate electrode.

### Claim 25 (depends on 24)

The method of claim 24, wherein the gate dielectric layer is further formed along sidewalls of the first dielectric spacer and the second dielectric spacer.