# US 10,121,874 B2 · Self-aligned bottom up gate contact and top down source-drain contact structure in the premetallization dielectric or interlevel dielectric layer of an integrated circuit

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,121,874 B2
- Document ID: US10121874B2
- Status: Granted
- Kind: B2
- Application number: 15/485,754
- Filed: 2017-04-12
- Published: 2017-08-03
- Granted: 2018-11-06
- Earliest claimed: 2015-06-09
- Assignees: STMicroelectronics S.r.l.
- Applicants: STMicroelectronics, Inc.
- Inventors: John Hongguang Zhang
- Web page: https://patentgrep.com/patent/US10121874B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6733: {Multi-gate TFTs}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10W 20/01: {Manufacture or treatment}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/43: Layouts of interconnections
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit includes a source-drain region, a channel region adjacent to the source-drain region, a gate structure extending over the channel region and a sidewall spacer on a side of the gate structure and which extends over the source-drain region. A dielectric layer is provided in contact with the sidewall spacer and having a top surface. The gate structure includes a gate electrode and a gate contact extending from the gate electrode as a projection to reach the top surface. The side surfaces of the gate electrode and a gate contact are aligned with each other. The gate dielectric layer for the transistor positioned between the gate electrode and the channel region extends between the gate electrode and the sidewall spacer and further extends between the gate contact and the sidewall spacer.

## Claims

### Claim 1

A method, comprising:
forming a dummy gate structure extending over a channel region, said dummy gate structure comprising a dummy gate electrode and sidewall spacers surrounding the dummy gate electrode and that extend over a source-drain region adjacent the channel region;
removing the dummy gate electrode to form a first opening between the sidewall spacers;
forming a replacement metal gate within the first opening, said replacement metal gate comprising a dielectric liner and a metal portion;
block masking a portion of the replacement metal gate where a gate contact is desired; and
recessing the replacement metal gate within the first opening except at said portion that is block masked to form a gate electrode where the replacement metal gate is recessed and further form said gate contact where the replacement metal gate is block masked.

### Claim 2 (depends on 1)

The method of claim 1, wherein recessing the replacement metal gate further forms a second opening over the gate electrode between the sidewall spacers where the replacement metal gate is recessed, and further comprising filling the second opening with an insulating material covering the gate electrode.

### Claim 3 (depends on 1)

The method of claim 1, wherein the dielectric liner is positioned between the gate electrode and the channel region, said dielectric liner extending between the gate electrode and the sidewall spacers and further extending between the gate contact and the sidewall spacers.

### Claim 4 (depends on 1)

The method of claim 1, wherein a side surface of the gate electrode and a side surface of the gate contact are aligned with each other and extend parallel to an inner surface of the sidewall spacers.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
providing a dielectric layer; and
forming a contact opening in the dielectric layer extending from a top surface of the dielectric layer to the source-drain region, said contact opening exposing an outer surface of the sidewall spacers, and filling said contact opening with a metal material to form a source-drain contact that is in contact with the outer surface of the sidewall spacers.

### Claim 6 (depends on 5)

The method of claim 5, wherein the dielectric layer is one of an interlevel dielectric (ILD) layer or pre-metallization dielectric (PMD) layer.

### Claim 7 (depends on 5)

The method of claim 5, wherein a height of the sidewall spacers is equal to a height of the dielectric layer.

### Claim 8 (depends on 5)

The method of claim 5, further comprising forming a metallization layer on a top surface of the dielectric layer, said metallization layer including a metal line in contact with said gate contact.

### Claim 9 (depends on 1)

The method of claim 1, further comprising using the block masking in performing an etch which thins the sidewall spacers at the gate contact.

### Claim 10 (depends on 1)

The method of claim 1, wherein the channel region and source-drain region are part of a fin of semiconductor material.

### Claim 11

A method, comprising:
forming a dummy gate structure extending over a channel region, said dummy gate structure comprising a dummy gate electrode and sidewall spacers surrounding the dummy gate electrode;
removing the dummy gate electrode to form a first opening between the sidewall spacers;
forming a replacement metal gate within the first opening, said replacement metal gate comprising a dielectric liner and a metal portion;
recessing a first portion of the replacement metal gate within the first opening to form a gate electrode, with a second portion of the replacement metal gate that is not recessed forming a gate contact; and
filling a second opening left by recessing the first of the replacement metal gate with an insulating material covering the gate electrode.

### Claim 12 (depends on 11)

The method of claim 11, wherein recessing the first portion comprises:
block masking the second portion of the replacement metal gate; and
etching the replacement metal gate except at said second portion that is block masked.

### Claim 13 (depends on 12)

The method of claim 12, wherein block masking comprises forming a block mask that covers said second portion of the replacement metal gate and further covers a portion of the sidewall spacers on opposite sides of the replacement metal gate, and further comprising recessing sidewall spacers except for the portion covered by the block mask.

### Claim 14 (depends on 13)

The method of claim 13, wherein recessing sidewall spacers further comprises recessing a portion of the insulating material covering the gate electrode.

### Claim 15 (depends on 11)

The method of claim 11, wherein the dielectric liner is positioned between the gate electrode and the channel region, said dielectric liner extending between the gate electrode and the sidewall spacers and further extending between the gate contact and the sidewall spacers.

### Claim 16 (depends on 11)

The method of claim 11, wherein a side surface of the gate electrode and a side surface of the gate contact are aligned with each other and extend parallel to an inner surface of the sidewall spacers.

### Claim 17 (depends on 11)

The method of claim 11, further comprising:
providing a dielectric layer; and
forming a contact opening in the dielectric layer extending from a top surface of the dielectric layer to a source-drain region adjacent the channel region, said contact opening exposing an outer surface of the sidewall spacers, and filling said contact opening with a metal material to form a source-drain contact that is in contact with the outer surface of the sidewall spacers.

### Claim 18 (depends on 17)

The method of claim 17, wherein the dielectric layer is one of an interlevel dielectric (ILD) layer or pre-metallization dielectric (PMD) layer.

### Claim 19 (depends on 17)

The method of claim 17, wherein a height of the sidewall spacers is equal to a height of the dielectric layer.

### Claim 20 (depends on 17)

The method of claim 17, further comprising forming a metallization layer on a top surface of the dielectric layer, said metallization layer including a metal line in contact with said gate contact.

### Claim 21 (depends on 11)

The method of claim 11, wherein the channel region and source-drain region are part of a fin of semiconductor material.

### Claim 22 (depends on 11)

The method of claim 11, further comprising providing a dielectric layer having a top surface coplanar with a top surface of the sidewall spacers, and wherein a top surface of the gate electrode is below the coplanar top surfaces of the dielectric layer and sidewall spacers, and wherein a top surface of the gate contact is coplanar with the coplanar top surfaces of the dielectric layer and sidewall spacers.

### Claim 23 (depends on 1)

The method of claim 1, further comprising providing a dielectric layer having a top surface coplanar with a top surface of the sidewall spacers, and wherein a top surface of the gate electrode is below the coplanar top surfaces of the dielectric layer and sidewall spacers, and wherein a top surface of the gate contact is coplanar with the coplanar top surfaces of the dielectric layer and sidewall spacers.