# US 10,121,873 B2 · Metal gate and contact plug design and method forming same

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- Number: US 10,121,873 B2
- Document ID: US10121873B2
- Status: Granted
- Kind: B2
- Application number: 15/429,894
- Filed: 2017-02-10
- Published: 2018-02-01
- Granted: 2018-11-06
- Earliest claimed: 2016-07-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chih-Teng Liao; Yi-Wei Chiu; Xi-Zong Chen; Chia-Ching Tsai
- Web page: https://patentgrep.com/patent/US10121873B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10P 50/268: {of silicon-containing layers}
- H10P 95/04: {Planarisation of conductive or resistive materials}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/076: {in via holes or trenches}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a dummy gate stack over a semiconductor region, forming a gate spacer on a sidewall of the dummy gate stack, removing the dummy gate stack to form an opening, forming a replacement gate stack in the opening, recessing the replacement gate stack to form a recess, filling the recess with a conductive material, and performing a planarization to remove excess portions of the conductive material over the gate spacer. A remaining portion of the conductive material forms a gate contact plug. A top portion of the gate contact plug is at a same level as a top portion of the first gate spacer.

## Claims

### Claim 1

A method comprising:
forming a first mask stack and a second mask stack having different widths;
forming a photo resist to cover the second mask stack;
trimming a first width of the first mask stack;
removing the photo resist;
further trimming the first width of the first mask stack and a second width of the second mask stack simultaneously; and
using the first mask stack and the second mask stack as an etching mask to etch a dummy gate electrode layer and a dummy gate dielectric layer as a dummy gate stack over a semiconductor region;
forming a first gate spacer on a sidewall of the dummy gate stack;
removing the dummy gate stack to form an opening;
forming a second gate spacer in the opening, wherein the second gate spacer has a first sidewall contacting the first gate spacer, and a bottom surface contacting a top surface of the semiconductor region;
forming a replacement gate stack in the opening, wherein the second gate spacer has a second sidewall contacting a sidewall of the replacement gate stack;
recessing the replacement gate stack to form a recess;
filling the recess with a conductive material; and
performing a planarization to remove excess portions of the conductive material over the first gate spacer, wherein a remaining portion of the conductive material forms a gate contact plug, wherein a top portion of the gate contact plug is at a same level as a top portion of the first gate spacer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the planarization is performed until the first gate spacer is exposed.

### Claim 3 (depends on 1)

The method of claim 1, wherein the removing the dummy gate stack comprises:
generating plasma from a fluorine-containing process gas;
filtering out ions from the plasma and leaving fluorine radicals; and
etching a polysilicon layer of the dummy gate stack using the fluorine radicals.

### Claim 4 (depends on 1)

The method of claim 1, wherein the forming the dummy gate stack over the semiconductor region comprises:
etching a dummy gate electrode layer to reveal a dummy gate dielectric layer; and
etching-through the dummy gate dielectric layer to expose the semiconductor region.

### Claim 5 (depends on 1)

The method of claim 1, wherein the gate contact plug comprises a sidewall contacting a sidewall of the first gate spacer.

### Claim 6 (depends on 1)

The method of claim 1, wherein both the replacement gate stack and the gate contact plug are in contact with a sidewall of the second gate spacer.

### Claim 7

A method comprising:
forming a dummy gate stack on a top surface and a sidewall of a semiconductor fin;
forming first gate spacers having sidewalls contacting sidewalls of the dummy gate stack;
forming a source/drain region on a side of the dummy gate stack;
forming an inter-layer dielectric to cover the source/drain region;
removing the dummy gate stack to form an opening between the first gate spacers;
forming a second gate spacer in the opening, wherein the second gate spacer has a first sidewall contacting a sidewall of one of the first gate spacers, and a second sidewall opposite to the first sidewall;
filling a bottom portion of the opening with a replacement gate stack; and
forming a gate contact plug to fill a top portion of the opening, wherein the gate contact plug is between top portions of the first gate spacers, wherein both the replacement gate stack and the gate contact plug are in contact with the second sidewall of the second gate spacer, and wherein the forming the gate contact plug comprises:
forming a sacrificial dielectric layer over the inter-layer dielectric;
etching the sacrificial dielectric layer to form an additional opening;
filling a metallic material into the additional opening and the top portion of the opening; and
performing a planarization on both the sacrificial dielectric layer and the metallic material, wherein the sacrificial dielectric layer is removed by the planarization.

### Claim 8 (depends on 7)

The method of claim 7, wherein the gate contact plug is formed by:
etching a top portion of the replacement gate stack to form a recess between the top portions of the first gate spacers;
filling the recess with a hard mask layer;
removing the hard mask layer to regenerate the recess;
filling the recess with a conductive material; and
performing a planarization to remove excess portions of the conductive material, with a remaining portion of the conductive material forming the gate contact plug.

### Claim 9 (depends on 7)

The method of claim 7, wherein the forming the replacement gate stack comprises:
filling a gate dielectric layer extending into the opening left by the removed dummy gate stack;
depositing a gate electrode layer over the gate dielectric layer; and
performing a planarization on the gate dielectric layer and the gate electrode layer to form the replacement gate stack.

### Claim 10 (depends on 7)

The method of claim 7 further comprising:
etching the inter-layer dielectric to form a source/drain contact opening, with the source/drain region exposed to the source/drain contact opening;
forming a source/drain contact plug to fill the source/drain contact opening, wherein when the gate contact plug is formed, a same material of the gate contact plug is deposited over and contacting the source/drain contact plug; and
removing a portion of the same material of the gate contact plug deposited over and contacting the source/drain contact plug.

### Claim 11 (depends on 7)

The method of claim 7, wherein the second gate spacer comprises a bottom surface contacting a top surface of the semiconductor fin.

### Claim 12 (depends on 7)

The method of claim 7 further comprising:
forming a first mask stack and a second mask stack having different widths;
forming a photo resist to cover the second mask stack;
trimming a first width of the first mask stack;
removing the photo resist;
further trimming the first width of the first mask stack and a second width of the second mask stack simultaneously; and
using the first mask stack and the second mask stack as an etching mask to etch a dummy gate electrode layer and a dummy gate dielectric layer as the dummy gate stack.

### Claim 13

A method comprising:
forming gate spacers over a semiconductor region;
forming a gate stack between the gate spacers, wherein the gate stack comprises:
a gate dielectric comprising a bottom portion and sidewall portion over and connected to opposite ends of the bottom portion; and
a gate electrode over the bottom portion of the gate dielectric;
forming an inter-layer dielectric on opposite sides of the gate stack, with the gate spacers in the inter-layer dielectric;
recessing the gate stack to form a recess;
filling a dielectric material into the recess;
planarizing the dielectric material and the gate spacers, wherein a remaining portion of the dielectric material forms a dielectric hard mask;
etching a first portion of the dielectric hard mask to form an opening;
forming a gate contact plug in the opening and between second portions of the dielectric hard mask, wherein the gate contact plug contacts top surfaces of the gate dielectric and the gate electrode, and wherein the forming the gate contact plug comprises:
forming a sacrificial dielectric layer over the inter-layer dielectric;
etching the sacrificial dielectric layer to form an additional opening;
filling a metallic material into the additional opening and the opening; and
performing a planarization on both the sacrificial dielectric layer and the metallic material, wherein the sacrificial dielectric layer is removed by the planarization; and
depositing an etch stop layer, wherein a bottom surface of the etch stop layer is in contact with top surfaces of the gate spacers, the inter-layer dielectric, and the gate contact plug.

### Claim 14 (depends on 13)

The method of claim 13, wherein the top surfaces of the gate spacers, the inter-layer dielectric, and the gate contact plug are substantially coplanar.

### Claim 15 (depends on 13)

The method of claim 13, wherein opposite edges of the gate contact plug are both in contact with the gate spacers.

### Claim 16 (depends on 13)

The method of claim 13, wherein a top surface of the dielectric hard mask is in contact with the bottom surface of the etch stop layer.

### Claim 17 (depends on 13)

The method of claim 13, wherein the forming the gate contact plug comprises planarizing the gate contact plug, the gate spacers, and the inter-layer dielectric.

### Claim 18 (depends on 13)

The method of claim 13 further comprising forming:
forming a dummy gate stack;
removing the dummy gate stack to form an opening between the gate spacers; and
forming an addition gate spacer in the opening, wherein the additional gate spacer has a bottom surface contacting a top surface of the semiconductor region.

### Claim 19 (depends on 18)

The method of claim 18, wherein both the gate stack and the gate contact plug are in contact with a sidewall of the additional gate spacer.

### Claim 20 (depends on 13)

The method of claim 13 further comprising:
forming a first mask stack and a second mask stack having different widths;
forming a photo resist to cover the second mask stack;
trimming a first width of the first mask stack;
removing the photo resist;
further trimming the first width of the first mask stack and a second width of the second mask stack simultaneously;
using the first mask stack and the second mask stack as an etching mask to etch a dummy gate electrode layer and a dummy gate dielectric layer as a dummy gate stack; and
replacing the dummy gate stack with the gate stack.