# US 10,121,872 B2 · Method for forming a semiconductor device comprising a selectively grown graphene layer

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- Number: US 10,121,872 B2
- Document ID: US10121872B2
- Status: Granted
- Kind: B2
- Application number: 15/683,106
- Filed: 2017-08-22
- Published: 2018-04-05
- Granted: 2018-11-06
- Earliest claimed: 2016-09-30
- Assignees: Semiconductor Manufacturing International (Beijing) Corporation; Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Semiconductor Manufacturing International (Beijing) Corporation; Semiconductor Manufacturing International (Shanghai) Corporation
- Inventors: Ming Zhou
- Web page: https://patentgrep.com/patent/US10121872B2

## CPC

- H10D 30/01: Manufacture or treatment
- H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs}
- H10D 30/017: {of FETs having two-dimensional material channels, e.g. TMD FETs}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 62/8303: {Diamond}
- H10D 62/882: {Graphene}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3238: {being insulating materials}
- H10P 14/3406: {Carbon, e.g. diamond-like carbon}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure relates to the technical field of semiconductor processes and discloses a semiconductor device and a manufacturing method therefor. The method includes: providing a substrate containing a first dielectric layer; forming a lower gate material layer on the first dielectric layer; patterning the lower gate material layer to form gate lines; depositing a second dielectric layer to cover the gate lines; planarizing the second dielectric layer; forming an insulating buffer material layer; patterning the insulating buffer material layer to form a patterned insulating buffer layer containing multiple separate portions, each separate portion extending to intersect one or more gate lines; selectively growing a graphene layer on the patterned insulating buffer layer; forming a third dielectric layer to cover the graphene layer and the second dielectric layer; and forming an upper gate electrode layer on the third dielectric layer. In the present disclosure, a patterned graphene layer may be obtained by means of the selective growth of graphene, thereby avoiding undesired effects from patterning the graphene. In addition, the semiconductor device of the present disclosure may use a dual-gate structure that can offer better current control.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising:
providing a substrate comprising a first dielectric layer;
forming a lower gate material layer on the first dielectric layer;
patterning the lower gate material layer to form gate lines;
depositing a second dielectric layer on the first dielectric layer and the gate lines to cover the gate lines;
planarizing the second dielectric layer to expose upper surfaces of the gate lines;
forming an insulating buffer material layer on the second dielectric layer and the gate lines;
patterning the insulating buffer material layer to form a patterned insulating buffer layer comprising multiple separate portions, each portion extending to intersect one or more gate lines;
selectively growing a graphene layer on the patterned insulating buffer layer;
forming a third dielectric layer to cover the graphene layer and the second dielectric layer; and
forming an upper gate electrode layer on the third dielectric layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the lower gate material layer comprises a polysilicon layer and a doped silicon germanium layer grown on the polysilicon layer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the lower gate material layer comprises a polysilicon layer, and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron formed on the polysilicon layer.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the graphene layer is selectively grown on the patterned insulating buffer layer at a temperature of 900-1000° C. by a chemical vapor deposition process using methane and hydrogen.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the insulating buffer material layer comprises an oxide of aluminum.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum.

### Claim 7 (depends on 1)

The method according to claim 1, further comprising patterning the upper gate electrode layer to form an upper gate electrode.

### Claim 8

A method for manufacturing a semiconductor device, comprising:
providing a substrate comprising a first dielectric layer;
forming a lower gate material layer on the first dielectric layer;
patterning the lower gate material layer to form gate lines;
depositing a second dielectric layer on the first dielectric layer and the gate lines to cover the gate lines;
planarizing the second dielectric layer to expose upper surfaces of the gate lines;
forming an insulating buffer material layer on the second dielectric layer and the gate lines;
patterning the insulating buffer material layer to form a patterned insulating buffer layer extending to intersect the gate lines;
forming a patterned fourth dielectric layer, wherein the patterned fourth dielectric layer covers a portion of the patterned insulating buffer layer and exposes separate portions of the patterned insulating buffer layer, where each exposed portion of the patterned insulating buffer layer intersects one or more gate lines;
selectively growing a graphene layer on the exposed portions of the patterned insulating buffer layer;
forming a third dielectric layer to cover the graphene layer and the fourth dielectric layer; and
forming an upper gate electrode layer on the third dielectric layer.

### Claim 9 (depends on 8)

The method according to claim 8, wherein the lower gate material layer comprises a polysilicon layer and a doped silicon germanium layer grown on the polysilicon layer, or a polysilicon layer, and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron formed on the polysilicon layer.

### Claim 10 (depends on 8)

The method according to claim 8, wherein the graphene layer is selectively grown on the patterned insulating buffer layer at a temperature of 900-1000° C. by a chemical vapor deposition process using methane and hydrogen.

### Claim 11 (depends on 8)

The method according to claim 8, wherein the insulating buffer material layer comprises an oxide of aluminum and the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum.

### Claim 12 (depends on 8)

The method according to claim 8, further comprising patterning the upper gate electrode layer to form an upper gate electrode.