# US 10,121,871 B2 · Semiconductor device and method for manufacturing semiconductor device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,121,871 B2
- Document ID: US10121871B2
- Status: Granted
- Kind: B2
- Application number: 15/386,872
- Filed: 2016-12-21
- Published: 2017-06-29
- Granted: 2018-11-06
- Earliest claimed: 2015-12-25
- Assignees: Rohm Co., Ltd.; Lapis Semiconductor Co., Ltd.
- Applicants: Rohm Co., Ltd.; LAPIS Semiconductor Co., Ltd.
- Inventors: Akihiro Hikasa; Kazusuke Kato
- Web page: https://patentgrep.com/patent/US10121871B2

## CPC

- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 8/411: {PN diodes having planar bodies}
- H10D 10/056: {of vertical BJTs having the main current going through the whole substrate, e.g. power BJTs}
- H10D 10/40: Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10D 64/111: {Field plates}
- H10D 64/23: Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 14/46: using a liquid
- H10D 62/8325: {Silicon carbide}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 72/07354: {changes in dispositions}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/381: {Auxiliary members}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device according to the present invention includes: a semiconductor layer including a first conductivity type semiconductor region and a second conductivity type semiconductor region joined to the first conductivity type semiconductor region; and a surface electrode connected to the second conductivity type region on one surface of the semiconductor layer, including a first Al-based electrode, a second Al-based electrode, a barrier metal interposed between the first Al-based electrode and the second Al-based electrode, and a plated layer on the second Al-based electrode.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor layer including a first conductivity type semiconductor region and a second conductivity type semiconductor region joined to the first conductivity type semiconductor region;
a surface electrode connected to the second conductivity type region on one surface of the semiconductor layer, including a first Al-based electrode being in direct contact with the second conductivity type semiconductor region, a second Al-based electrode, a barrier metal interposed between the first Al-based electrode and the second Al-based electrode, and a plated layer on the second Al-based electrode; and
an insulating layer being in direct contact with the second conductivity type semiconductor region,
wherein the first Al-based electrode has an extending portion extending along an upper surface of the insulating layer and being in direct contact with the upper surface, and
the extending portion of the first Al-based electrode has an end portion on the upper surface of the insulating layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the second Al-based electrode has fine irregularities in at least a portion of the boundary with the plated layer.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the second Al-based electrode is thicker than the first Al-based electrode.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the first Al-based electrode has a thickness of 0.5 μm to 3.0 μm, and the second Al-based electrode has a thickness of 3.0 μm to 6.0 μm.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the barrier metal has a thickness of 0.02 μm to 0.5 μm.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the plated layer has a thickness of 2.0 μm to 5.0 μm.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the first Al-based electrode is made of at least one material selected from a group of Al, Al Si, AlCu, and AlSiCu.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the second Al-based electrode is made of at least one material selected from a group of Al, Al Si, AlCu, and AlSiCu.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the barrier metal is made of at least one material selected from a group of TiN, Ti, TiSi2, TiW, W, WSi, WSi2, Pd, Ni, NiSi2, Cr, CrSi2, Cr2N, Co, CoSi2, Pt, Mo, MoSi, Mo2N, Cu, Ta, TaSi2, Nb, Fe, and Cu.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein the plated layer has an Ni layer on at least a portion in contact with the second Al-based electrode.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor device includes a pn diode.

### Claim 12 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor device includes an IGBT.

### Claim 13 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor device includes a MISFET.

### Claim 14 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor device includes a bipolar transistor.

### Claim 15 (depends on 1)

The semiconductor device according to claim 1,
wherein the barrier metal has an extending portion extending along the upper surface of the insulating layer, and
the extending portion of the barrier metal has an end portion above the upper surface of the insulating layer.

### Claim 16 (depends on 1)

The semiconductor device according to claim 1,
wherein the second Al-based electrode has an extending portion extending along the upper surface of the insulating layer, and
the extending portion of the second Al-based electrode has an end portion above the upper surface of the insulating layer.

### Claim 17 (depends on 1)

The semiconductor device according to claim 1,
wherein the first Al-based electrode has a contact portion which is in direct contact with the second conductivity type semiconductor region, and
a surface of the extending portion of the first Al-based electrode facing the barrier metal is positioned at a higher position than a surface of the contact portion of the first Al-based electrode facing the barrier metal.

### Claim 18

A method for manufacturing a semiconductor device comprising:
a step of forming an insulating layer on one surface of a semiconductor layer including a first conductivity type semiconductor region, and a second conductivity type semiconductor region joined to the first conductivity type semiconductor region so as to be directly contacted with the second conductivity type semiconductor region and expose a part of the second conductivity type semiconductor region;
a step of forming a first Al-based electrode on the one surface of the semiconductor layer so as to be connected to the second conductivity type semiconductor region;
a step of forming a barrier metal on the first Al-based electrode;
a step of forming a second Al-based electrode on the barrier metal; and
a step of forming a plated layer on the second Al-based electrode by electroless plating,
wherein in the step of forming the first Al-based electrode, the first Al-based electrode is formed so as to have an extending portion extending along an upper surface of the insulating layer and be in direct contact with the upper surface.

### Claim 19 (depends on 18)

The method for manufacturing a semiconductor device according to claim 18, further comprising a step of annealing the first Al-based electrode prior to the formation of the barrier metal.

### Claim 20 (depends on 18)

The method for manufacturing a semiconductor device according to claim 18, further comprising a step of etching the surface of the second Al-based electrode using an alkaline-based agent prior to the formation of the plated layer.