# US 10,121,870 B1 · Semiconductor device structure with strain-relaxed buffer

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,121,870 B1
- Document ID: US10121870B1
- Status: Granted
- Kind: B1
- Application number: 15/692,169
- Filed: 2017-08-31
- Granted: 2018-11-06
- Earliest claimed: 2017-08-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hung-Li Chiang; I-Sheng Chen; Tzu-Chiang Chen
- Web page: https://patentgrep.com/patent/US10121870B1

## CPC

- H10D 64/519: {characterised by their top-view geometrical layouts}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 62/364: {of IGFETs}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Semiconductor device structures are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes semiconductor wires stacked over the fin structure. The semiconductor device structure further includes a gate stack over the fin structure. The semiconductor wires are surrounded by the gate stack. In addition, the semiconductor device structure includes source or drain structures over the fin structure and on opposite sides of the semiconductor wires. The semiconductor device structure also includes strain-relaxed buffer structures between the source or drain structures and the fin structure. The strain-relaxed buffer structures and the semiconductor wires have different lattice constants.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a fin structure over a semiconductor substrate;
semiconductor wires stacked over the fin structure;
a gate stack over the fin structure, wherein the semiconductor wires are surrounded by the gate stack;
source or drain structures over the fin structure and on opposite sides of the semiconductor wires;
strain-relaxed buffer structures between the source or drain structures and the fin structure, wherein the strain-relaxed buffer structures and the semiconductor wires have different lattice constants; and
an isolation feature surrounding the fin structure and the strain-relaxed buffer structures, wherein the strain-relaxed buffer structures protrude from a top surface of the isolation feature.

### Claim 2 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the strain-relaxed buffer structures have a V-shaped bottom.

### Claim 3 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
first spacer elements over the fin structure and on opposite sides of the gate stack; and
second spacer elements between the semiconductor wires.

### Claim 4 (depends on 3)

The semiconductor device structure as claimed in claim 3, wherein the second spacer elements are narrower than the first spacer elements.

### Claim 5 (depends on 3)

The semiconductor device structure as claimed in claim 3, wherein the first spacer elements and the second spacer elements comprise different dielectric materials.

### Claim 6 (depends on 3)

The semiconductor device structure as claimed in claim 3, wherein the source or drain structures are in contact with the semiconductor wires, the first spacer elements and the second spacer elements.

### Claim 7 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the semiconductor wires are narrower than the fin structure.

### Claim 8 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the semiconductor wires comprise a semiconductor material, and the source or drain structures comprise the semiconductor material.

### Claim 9 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the strain-relaxed buffer structures are embedded in the fin structure.

### Claim 10

A semiconductor device structure, comprising:
a first transistor over a semiconductor substrate, wherein the first transistor comprises:
first semiconductor wires having a first lattice constant;
a first gate stack surrounding the first semiconductor wires;
first spacer elements over the first semiconductor wires and on opposite sides of the first gate stack;
second spacer elements between the first semiconductor wires; and
first composite source or drain regions on opposite sides of the first semiconductor wires, wherein the first composite source or drain regions comprise a first buffer structure and a first source or drain structure covering the first buffer structure, and wherein the first buffer structure has a second lattice constant that is different from the first lattice constant; and
a second semiconductor wire between the first semiconductor wires, wherein the second semiconductor wire is separated from the first source or drain region structure.

### Claim 11 (depends on 10)

The semiconductor device structure as claimed in claim 10, further comprising a second transistor over the semiconductor substrate, wherein the second transistor comprises:
second semiconductor wires having the first lattice constant;
a second gate stack surrounding the second semiconductor wires; and
second composite source or drain regions on opposite sides of the second semiconductor wires, wherein the second composite source or drain regions comprise a second buffer structure and a second source or drain structure covering the second buffer structure, and wherein the second buffer structure has a third lattice constant that is different from the first lattice constant.

### Claim 12 (depends on 11)

The semiconductor device structure as claimed in claim 11, wherein the third lattice constant is different from the first lattice constant and the second lattice constant.

### Claim 13 (depends on 10)

The semiconductor device structure as claimed in claim 10, further comprising a second transistor over the semiconductor substrate, wherein the second transistor comprises:
second semiconductor wires having the first lattice constant;
a second gate stack surrounding the second semiconductor wires; and
second source or drain regions on opposite sides of the second semiconductor wires, wherein the first source or drain structure has the first lattice constant, and the second source or drain regions has a third lattice constant that is different from the first lattice constant.

### Claim 14 (depends on 13)

The semiconductor device structure as claimed in claim 13, wherein the first composite source or drain regions and the second source or drain regions have a V-shaped bottom.

### Claim 15 (depends on 13)

The semiconductor device structure as claimed in claim 13, wherein bottoms of the first composite source or drain regions and the second source or drain regions are different shapes.

### Claim 16 (depends on 10)

The semiconductor device structure as claimed in claim 10, further comprising an isolation feature over the semiconductor substrate and below the first source or drain structure, wherein the first buffer structure protrude from a top surface of the isolation feature.

### Claim 17

A semiconductor device structure, comprising:
a fin structure over a semiconductor substrate;
a source or drain structure over the fin structure;
a strain-relaxed buffer structure between the source or drain structure and the fin structure;
an isolation feature over the semiconductor substrate and below the source or drain structure, wherein the isolation feature surrounds the fin structure and the strain-relaxed buffer structure;
a dielectric layer covering the isolation feature and surrounding the source or drain structure; and
an isolation liner between the isolation feature and the fin structure, wherein the isolation liner further extends between the isolation feature and the strain-relaxed buffer structure.

### Claim 18 (depends on 17)

The semiconductor device structure as claimed in claim 17, wherein the source or drain structure is wider than the strain-relaxed buffer structure.

### Claim 19 (depends on 17)

The semiconductor device structure as claimed in claim 17, wherein a width of the strain-relaxed buffer structure is substantially equal to a width of the fin structure.

### Claim 20 (depends on 17)

The semiconductor device structure as claimed in claim 17, wherein the strain-relaxed buffer structure and the fin structure have different lattice constants.