# US 10,121,869 B2 · Method of manufacturing semiconductor memory device

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- Number: US 10,121,869 B2
- Document ID: US10121869B2
- Status: Granted
- Kind: B2
- Application number: 15/832,733
- Filed: 2017-12-05
- Published: 2018-04-19
- Granted: 2018-11-06
- Earliest claimed: 2016-08-04
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corporation
- Inventors: Weichang Liu; Zhen Chen; Shen-De Wang; Wang Xiang; Wei Ta
- Web page: https://patentgrep.com/patent/US10121869B2

## CPC

- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10B 43/30: characterised by the memory core region
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/691: {having more than two programming levels}
- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge.

## Claims

### Claim 1

A method of manufacturing a semiconductor memory device comprising:
providing a substrate;
forming a plurality of gate structures and a plurality of dielectric caps, wherein the gate structures are formed on the substrate and each gate structure comprise a first gate and a first gate dielectric layer, the first gate dielectric layer disposed between the first gate and the substrate, and the dielectric caps are formed atop the gate structures respectively;
forming a first dielectric layer covering the dielectric caps and a plurality of sidewalls of the gate structures;
forming a second dielectric layer covering the first dielectric layer, wherein materials of both the first dielectric layer and the second dielectric layer are different;
partially removing the second dielectric layer to reveal a plurality of top parts of the first dielectric layer and to form a plurality of first spacing films;
forming a plurality of second gates on the substrate, wherein the second gates covering and contacting the first dielectric layer and a top edge of the first spacing film;
removing the dielectric caps to reveal the first gates; and
forming a plurality of drains and a plurality of sources in the substrate.

### Claim 2 (depends on 1)

The method according to claim 1, wherein partially removing the second dielectric layer comprises performing a plasma etching.

### Claim 3 (depends on 1)

The method according to claim 1, wherein removing the dielectric caps comprise performing a wet etching.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the substrate, the first gate dielectric layer, and the first gate form a SONOS structure.

### Claim 5 (depends on 1)

The method according to claim 1, further comprising partially removing the first dielectric layer to reveal the dielectric caps after forming the second gates.

### Claim 6 (depends on 1)

The method according to claim 1, further comprising forming an electric isolating structure in the substrate before forming the gate structures and the dielectric caps.