# US 10,121,867 B2 · Semiconductor structure and associated fabricating method

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- Number: US 10,121,867 B2
- Document ID: US10121867B2
- Status: Granted
- Kind: B2
- Application number: 15/147,635
- Filed: 2016-05-05
- Published: 2017-07-06
- Granted: 2018-11-06
- Earliest claimed: 2015-12-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Hong-Shyang Wu; Kuo-Ming Wu
- Web page: https://patentgrep.com/patent/US10121867B2

## CPC

- H10D 64/118: {Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 64/111: {Field plates}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.

## Claims

### Claim 1

A semiconductor structure, comprising:
a gate structure formed on a substrate;
a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity;
a dielectric layer contiguously extending from over the gate structure to over the drain region, the dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer extends from the first portion toward the drain region, wherein the dielectric layer includes a plurality of recesses, and wherein each recess of the plurality of recesses is arranged in a line parallel to a width of the gate structure; and
a trench filled with conductive material extending to the drain region, wherein at least one recess of the plurality of recesses is between the trench and the gate structure.

### Claim 2 (depends on 1)

The semiconductor structure claim 1, wherein sidewall spaces are formed on each side of the gate structure and wherein the sidewall spacers on a first side of the gate structure are between the gate structure and the plurality of recesses.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the at least one recess of the plurality of recesses is over a portion of a well region of the substrate disposed between the drain region and the sidewall spacer on the first side of the gate structure.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the at least one recess has a bottom exposing a top surface of the well region under the dielectric layer.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein a ratio of a width of the at least one recess to a width of the second portion of the dielectric layer is in a range from about 0.2 to about 0.3.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein a ratio of a depth of the at least one recess to a thickness of the second portion of the dielectric layer is in a range from about 0 to about 0.8.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the plurality of recesses includes two neighboring recesses and wherein a ratio of a spacing between the two neighboring recesses to a width of each of the neighboring recesses is in a range from about 1 to about 1.2.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein each recess of the plurality of recesses is square-shaped.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the at least one recess of the dielectric layer includes an elongated rectangular recess.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein the semiconductor structure is a high voltage device.

### Claim 11 (depends on 1)

The semiconductor structure of claim 1, wherein the first type includes an n-type semiconductor material.

### Claim 12

A semiconductor structure, comprising:
a gate structure formed on a substrate;
a source region disposed on a first side of the gate structure and a drain region formed in the substrate on a second side of the gate structure, the source region and the drain region both having a first type of conductivity;
a dielectric layer contiguously extending from over the gate structure over a region of the substrate extending between the second side of the gate structure and the drain region, and extending to over the drain region, wherein the dielectric layer includes at least one recess in a portion of the dielectric layer over the region of the substrate extending between the second side of the gate structure and the drain region, the at least one recess being spaced a distance from the second side of the gate toward the drain region; and
an interlayer dielectric (ILD) layer formed on the substrate, the ILD layer including a first trench extending through the ILD layer to the at least one recess, wherein the first trench is substantially filled with a conductive material and a second trench extending through the ILD layer to a silicide region of the drain region, wherein the second trench is substantially filled with the conductive material.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein the conductive material in the first trench further substantially fills the at least one recess.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13, wherein the conductive material is coupled to the source region through a multilayer interconnect (MLI) structure.

### Claim 15 (depends on 12)

The semiconductor structure of claim 12, wherein the semiconductor structure is a high voltage device.

### Claim 16 (depends on 12)

The semiconductor structure of claim 12, wherein the ILD layer includes a third trench filled with the conductive material and extending to the gate structure, wherein the first trench is between the second and third trenches.

### Claim 17 (depends on 12)

The semiconductor structure of claim 12, wherein the drain region includes an implanted region of the substrate.

### Claim 18 (depends on 12)

The semiconductor structure of claim 12, wherein the at least one recess includes a plurality of recesses disposed in a line parallel to a width of the gate structure.

### Claim 19

A semiconductor structure, comprising a gate structure having gate spacers from on a substrate, wherein the gate structure has a length and a width, the greater than the length; a source region and a drain region formed in the substrate on either of the gate structure, wherein the drain region includes a silicide portion; a dielectric layer extending over a portion of the gate structure and over the drain region, wherein the dielectric layer has a plurality of the recesses in a portion of the dielectric layer that is over a region of the substrate between the gate spacers of the gate structure nearest the drain region and the silicide portion of the drain region, the plurality of recesses being collinear and being disposed along the width of the gate structure; a first conductive element providing contact to the silicide portion of the drain region; a second conductive element providing contact to the gate structure; and a third conductive element providing contact to the plurality of recesses, wherein portions of an interlayer dielectric (ILD) layer are between each of the first, second and third conductives.