# US 10,121,866 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,866 B2 - Document ID: US10121866B2 - Status: Granted - Kind: B2 - Application number: 15/421,371 - Filed: 2017-01-31 - Published: 2017-08-17 - Granted: 2018-11-06 - Earliest claimed: 2016-02-16 - Assignees: Fuji Electric Co., Ltd. - Applicants: Fuji Electric Co., Ltd. - Inventors: Tatsuya Naito - Web page: https://patentgrep.com/patent/US10121866B2 ## CPC - H10D 62/60: Impurity distributions or concentrations - G01K 7/01: using semiconducting elements having PN junctions (G01K7/02, G01K7/16, G01K7/30 take precedence) - G01K 13/00: Thermometers specially adapted for specific purposes - H10D 8/422: {PN diodes having the PN junctions in mesas} - H10D 12/441: {Vertical IGBTs} - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices} - H10D 62/53: the imperfections being within the semiconductor body - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D 84/617: {Combinations of vertical BJTs and only diodes} - H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)} - H10D 64/112: {comprising multiple field plate segments} - H10P 32/171: {being group IV material} - H10P 32/18: {Diffusion lifetime killers} - H10W 72/926: {Multiple bond pads having different sizes} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G01K: MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR (radiation pyrometry G01J5/00) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Provided is a semiconductor device having an RC-IGBT structure, the semiconductor device comprising an FWD (Free Wheel Diode) region and an IGBT (Insulated Gate Bipolar Transistor) region. Provided is a semiconductor device comprising: a semiconductor substrate; a transistor section formed on the semiconductor substrate; a diode section formed on the semiconductor substrate and including a lifetime killer at a front surface side of the semiconductor substrate; a gate runner provided between the transistor section and the diode section and electrically connected to a gate of the transistor section. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor substrate; a transistor section formed on the semiconductor substrate; a diode section formed on the semiconductor substrate and including a lifetime killer at a front surface side of the semiconductor substrate; and a gate runner provided between the transistor section and the diode section and electrically connected to a gate of the transistor section, a well region having a conductivity type different from that of the semiconductor substrate and formed below the gate runner such that the well region overlaps the transistor section, the transistor section thereby having an overlapping region and a non-overlapping region, wherein the semiconductor substrate includes the lifetime killer in a substantially entire region below the gate runner at the front surface side of the semiconductor substrate. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor substrate includes the lifetime killer in an entire region at the front surface side of the semiconductor substrate and below the gate runner. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor substrate includes the lifetime killer in at least a portion at the front surface side of the semiconductor substrate and closer to the transistor section than to the gate runner. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein a collector region of the transistor section is formed in at least a portion below the gate runner. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein a collector region of the transistor section is formed in an entire region below the gate runner. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein a collector region of the transistor section is formed at least a portion closer to the diode section than to the gate runner. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein a cathode region of the diode section is not formed below the gate runner. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the transistor section includes a gate trench section formed on the front surface of the semiconductor substrate, and at least a portion of the gate trench section is formed below the gate runner. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the diode section is arranged at an end portion of an active region of the semiconductor device. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the diode section is arranged at a corner portion of an active region of the semiconductor device. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the diode section surrounds the transistor section in a planar view. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein the transistor section surrounds the diode section in a planar view. ### Claim 13 (depends on 1) The semiconductor device according to claim 1 further comprising: a temperature sensor provided adjacent to the transistor section to detect signals in response to a temperature of the transistor section; and a temperature sensor terminal electrically connected to the temperature sensor through a wiring for sensors, to which the signals detected by the temperature sensor are input. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein the diode section includes an isolation region to allow at least one of the gate runner and the wiring for sensors to traverse the diode section. ### Claim 15 (depends on 13) The semiconductor device according to claim 13, wherein the temperature sensor is arranged above a well region. ### Claim 16 (depends on 13) The semiconductor device according to claim 13, wherein the temperature sensor is surrounded by the transistor section. ### Claim 17 (depends on 13) The semiconductor device according to claim 13, wherein the diode section includes: a first diode region formed at one end of an active region of the semiconductor device; and a second diode region formed at the other end of the active region opposing to the one end. ### Claim 18 (depends on 17) The semiconductor device according to claim 17, wherein the temperature sensor is provided between the first diode region and the second diode region. ### Claim 19 (depends on 1) The semiconductor device according to claim 1 further comprising: an emitter region of a first conductivity type formed on the front surface of the semiconductor substrate; a base region of a second conductivity type which is different from the first conductivity type formed on the front surface of the semiconductor substrate; an accumulating layer of the first conductivity type formed at the front surface side of the semiconductor substrate and having a higher concentration than an impurity concentration of the semiconductor substrate; and an interlayer insulating film formed on the front surface of the semiconductor substrate; wherein the interlayer insulating film includes a contact hole corresponding to at least some regions of the emitter region and the base region and formed to penetrate the interlayer insulating film, and the accumulating layer is formed inside a region in which the contact hole is formed in an extending direction of a trench section included in the transistor section. ### Claim 20 (depends on 19) The semiconductor device according to claim 19, wherein the accumulating layer is formed inside a region in which the contact hole is formed in an extending direction of a trench section included in the diode section. ### Claim 21 (depends on 19) The semiconductor device according to claim 19, wherein the accumulating layer is formed in a region in which the transistor section, the diode section and the gate runner are formed. ### Claim 22 (depends on 19) The semiconductor device according to claim 19, wherein at least a portion of the accumulating layer is formed within a well region. ### Claim 23 (depends on 19) The semiconductor device according to claim 19, wherein the contact hole at the diode section side is formed to be apart from a well region in a planar view. ### Claim 24 (depends on 1) The semiconductor device according to claim 1, wherein at least a portion of an end portion of a trench section of the transistor section is formed within a well region. ### Claim 25 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor substrate does not include a lifetime killer in substantially the entire non-overlapping region of the transistor section at the front surface side of the semiconductor substrate. ### Claim 26 (depends on 1) The semiconductor device according to claim 1, wherein the diode section is a free wheel diode section. ### Claim 27 (depends on 1) The semiconductor device according to claim 1, further comprising an anode region formed at the front surface side of the semiconductor substrate; and a cathode region formed at the back surface side of the semiconductor substrate.