# US 10,121,863 B2 · Semiconductor device and method manufacturing the same

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- Number: US 10,121,863 B2
- Document ID: US10121863B2
- Status: Granted
- Kind: B2
- Application number: 15/631,993
- Filed: 2017-06-23
- Published: 2018-06-14
- Granted: 2018-11-06
- Earliest claimed: 2016-12-13
- Assignees: Hyundai Motor Company; Kia Motors Corporation
- Applicants: Hyundai Motor Company; Kia Motors Corporation
- Inventors: NackYong Joo; Youngkyun Jung; Junghee Park; JongSeok Lee; Dae Hwan Chun
- Web page: https://patentgrep.com/patent/US10121863B2

## CPC

- H10D 62/8325: {Silicon carbide}
- H10D 12/031: {of IGBTs}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/635: {having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs}
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 48/01: Manufacture or treatment
- H10D 62/8303: {Diamond}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 84/141: {VDMOS having built-in components}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device may include an n− type layer sequentially disposed at a first surface of an n+ type silicon carbide substrate; a p type region disposed in the n− type layer; an auxiliary n+ type region disposed on the p type region or in the p type region; an n+ type region disposed in the p type region; an auxiliary electrode disposed on the auxiliary n+ type region and the p type region; a gate electrode separated from the auxiliary electrode and disposed on the n− type layer; a source electrode separated from the auxiliary electrode and the gate electrode; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate, wherein the auxiliary n+ type region and the n+ type region are separated from each other, and the source electrode is in contact with the n+ type region.

## Claims

### Claim 1

A semiconductor device comprising:
an n− type layer disposed at a first surface of an n+ type silicon carbide substrate;
a p type region disposed in the n− type layer;
an auxiliary n+ type region disposed on the p type region or in the p type region;
an n+ type region disposed in the p type region;
an auxiliary electrode disposed on the auxiliary n+ type region and the p type region;
a gate electrode separated from the auxiliary electrode and disposed on the n− type layer;
a source electrode separated from the auxiliary electrode and the gate electrode; and
a drain electrode disposed at a second surface of the n+ type silicon carbide substrate,
wherein the auxiliary n+ type region and the n+ type region are separated from each other, and
the source electrode is in contact with the n+ type region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein
the auxiliary electrode is in contact with the p type region.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further including:
a first trench disposed at the n− type layer; and
a gate insulating layer disposed in the first trench.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein
the gate electrode is disposed in the first trench, and
the auxiliary n+ type region is disposed adjacent to a side surface of the first trench.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein
the p type region is disposed adjacent to the side surface of the first trench.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, further including:
an insulating layer disposed between the gate electrode and the auxiliary electrode, and the source electrode.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further including:
a second trench disposed at the n− type layer and separated from the first trench.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein
the p type region is disposed adjacent to a side surface of the second trench and extends below a lower surface of the second trench.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein
the n+ type region is disposed under the lower surface of the second trench.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein
the auxiliary electrode extends from above the auxiliary n+ type region to the lower surface of the second trench via the side surface of the second trench.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, further including:
a gate insulating layer disposed on the n− type layer, the p type region, and the auxiliary n+ type region.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein
the gate electrode is disposed on the gate insulating layer, and
the auxiliary electrode is disposed at a side surface of the gate insulating layer.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, further including:
an insulating layer disposed between the gate electrode and the auxiliary electrode, and the source electrode.

### Claim 14

A method for manufacturing a semiconductor device comprising:
forming an n− type layer at a first surface of an n+ type silicon carbide substrate;
etching the n− type layer to form a first trench and a second trench thereon;
forming a p type region adjacent to a side surface of the second trench and extending to a lower surface of the second trench;
forming an auxiliary n+ type region on the p type region and the n− type layer;
forming an n+ type region separated from the auxiliary n+ type region and disposed in the p type region;
forming an auxiliary electrode on the auxiliary n+ type region;
forming a gate insulating layer in the first trench;
forming a gate electrode on the gate insulating layer;
forming an insulating layer on the gate electrode and the auxiliary electrode;
forming a source electrode on the insulating layer and the n+ type region; and
forming a drain electrode at a second surface of the n+ type silicon carbide substrate,
wherein the auxiliary electrode is separated from the gate electrode and the source electrode, and
wherein the source electrode is in contact with the n+ type region,
wherein the semiconductor device includes:
the n− type layer disposed at the first surface of the n+ type silicon carbide substrate;
the p type region disposed in the n− type layer;
the auxiliary n+ type region disposed on the p type region or in the p type region;
the n+ type region disposed in the p type region;
the auxiliary electrode disposed on the auxiliary n+ type region and the p type region;
the gate electrode separated from the auxiliary electrode and disposed on the n− type layer;
the source electrode separated from the auxiliary electrode and the gate electrode; and
the drain electrode disposed at the second surface of the n+ type silicon carbide substrate,
wherein the auxiliary n+ type region and the n+ type region are separated from each other, and
the source electrode is in contact with the n+ type region.

### Claim 15 (depends on 14)

The method of claim 14, wherein
the auxiliary electrode is in contact with the p type region.

### Claim 16 (depends on 15)

The method of claim 15, wherein
the n+ type region is disposed under the lower surface of the second trench.

### Claim 17 (depends on 16)

The method of claim 16, wherein
the auxiliary electrode extends from above the auxiliary n+ type region to the lower surface of the second trench via the side surface of the second trench.